SSTUM32868ET/G NXP [NXP Semiconductors], SSTUM32868ET/G Datasheet - Page 14

• Manufacturer Part Number: SSTUM32868ET/G
• Description: 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SSTUM32868_2
Product data sheet
Fig 6. Timing diagram during start-up (RESET switches from LOW to HIGH)
Dn, DODTn,
Qn, QODTn,
PAR_IN
DCKEn
(1) After RESET is switched from LOW to HIGH, all data and PAR_IN input signals must be set and held LOW for a minimum
(2) If the data is clocked on the m clock pulse, and PAR_IN is clocked in at m + 1, the QERR output signal will be produced on
QERR
CSGEN
RESET
QCKEn
DCSn
time of t
the m + 2 clock pulse and it will be valid on the m + 3 clock pulse.
CK
CK
(1)
(1)
(2)
ACT(max)
7.3 Register timing
HIGH, LOW, or Don't care
to avoid false error.
t
ACT
m
HIGH or LOW
t
PDM
Rev. 02 — 2 March 2007
, t
CK to Q
PDMSS
1.8 V DDR2-800 configurable registered buffer with parity
t
su
data to QERR latency
m + 1
t
h
CK to QERR
t
su
t
PHL
m + 2
t
h
SSTUM32868
m + 3
CK to QERR
t
PHL
, t
© NXP B.V. 2007. All rights reserved.
PLH
m + 4
002aab899
14 of 30