SSTUM32868ET/G NXP [NXP Semiconductors], SSTUM32868ET/G Datasheet - Page 12

• Manufacturer Part Number: SSTUM32868ET/G
• Description: 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SSTUM32868_2
Product data sheet
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (floating) data, clock, and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset and
all outputs are forced LOW except QERR. The LVCMOS RESET and C inputs always
must be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be ensured between the two.
When entering reset, the register will be cleared and the data outputs will be driven LOW
quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUM32868 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
The SSTUM32868 includes a parity checking function. Parity, which arrives one cycle
after the data input to which it applies, is checked on the PAR_IN input of the device. The
corresponding QERR output signal for the data inputs is generated two clock cycles after
the data, to which the QERR signal applies, is registered.
The SSTUM32868 accepts a parity bit from the memory controller on the parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D inputs
(D1 to D5, D7, D9 to D12, D17 to D28 when C = 0; or D1 to D12, D17 to D20, D22, D24 to
D28 when C = 1) and indicates whether a parity error has occurred on the open-drain
QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an
even number of ones across the DIMM-independent data inputs combined with the parity
input bit. To calculate parity, all DIMM-independent D inputs must be tied to a known logic
state.
If an error occurs and the QERR output is driven LOW, it stays latched LOW for a
minimum of two clock cycles or until RESET is driven LOW. If two or more consecutive
parity errors occur, the QERR output is driven LOW and latched LOW for a clock duration
equal to the parity error duration or until RESET is driven LOW. If a parity error occurs on
the clock cycle before the device enters the Low-Power Mode (LPM) and the QERR
output is driven LOW, then it stays latched LOW for the LPM duration plus two clock cycles
or until RESET is driven LOW. The DIMM-dependent signals (DCKE0, DCKE1, DODT0,
DODT1, DCS0, DCS1, DCS2 and DCS3) are not included in the parity check
computation.
The C input controls the pinout configuration from Register A configuration (when LOW) to
Register B configuration (when HIGH). The C input should not be switched during normal
operation. It should be hard-wired to a valid LOW or HIGH level to configure the register in
the desired mode.
The device also supports low-power active operation by monitoring both system chip
select (DCS0, DCS1, DCS2 and DCS3) and CSGEN inputs and will gate the Qn outputs
from changing states when CSGEN, DCS0 and DCS1 inputs are HIGH. If CSGEN or the
DCSn inputs are LOW, the Qn outputs will function normally. Also, if all DCSn inputs are
HIGH, the device will gate the QERR output from changing states. If any of the DCSn are
Rev. 02 — 2 March 2007
1.8 V DDR2-800 configurable registered buffer with parity
SSTUM32868
© NXP B.V. 2007. All rights reserved.
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