SSTUM32868ET/G NXP [NXP Semiconductors], SSTUM32868ET/G Datasheet - Page 11

• Manufacturer Part Number: SSTUM32868ET/G
• Description: 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 4.
[1]
[2]
Table 5.
[1]
[2]
[3]
[4]
[5]
SSTUM32868_2
Product data sheet
RESET
RESET
H
H
Q
DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs.
DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function.
PAR_IN arrives one clock cycle after the data to which it applies.
This transition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
QERR
If DCS0, DCS1, DCS2, DCS3 and CSGEN are driven HIGH, the device is placed in Low-Power Mode (LPM). If a parity error occurs on
the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays latched LOW for the LPM duration plus
two clock cycles or until RESET is driven LOW.
L
H
H
H
H
H
H
H
H
H
H
L
0
is the previous state of the associated output.
0
is the previous state of output QERR.
Function table (each flip-flop)
Parity and standby function table
DCS0
floating
X or floating
X or
DCS0
H
H
7.2 Functional information
[2]
X
X
X
X
H
X
L
L
L
L
[1]
DCS1
floating
The SSTUM32868 is a 28-bit 1 : 2 configurable registered buffer designed for 1.7 V to
1.9 V V
All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select
gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All
outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet
SSTL_18 specifications, except the open-drain error (QERR) output.
X or
H
H
X or floating
[2]
DCS1
DD
H
X
X
X
X
X
L
L
L
L
X or floating
[1]
operation.
CSGEN
Inputs
H
H
X or floating
…continued
L or H
CK
Inputs
floating
Rev. 02 — 2 March 2007
L or H
X or
CK
1.8 V DDR2-800 configurable registered buffer with parity
X or floating
L or H
floating
CK
L or H
X or
CK
Dn, DODTn,
X or floating
DCKEn
(D1 to D28)
of inputs = H
H
X
even
even
even
even
odd
odd
odd
odd
X
X
X
Qn
Q
Q
L
0
0
SSTUM32868
X or floating
PAR_IN
QCS0x QCS1x
Q
H
L
H
H
H
H
L
L
L
L
X
X
0
Outputs
[2]
© NXP B.V. 2007. All rights reserved.
Q
H
L
0
[1]
QERR
QERR
Output
QERR
QODTn,
QCKEn
H
H
H
H
H
L
L
L
L
[3][4]
11 of 30
Q
0
H
L
[5]
0
0