SSTUM32868ET/G NXP [NXP Semiconductors], SSTUM32868ET/G Datasheet - Page 16

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SSTUM32868ET/G

Manufacturer Part Number
SSTUM32868ET/G
Description
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
SSTUM32868_2
Product data sheet
Fig 8. Timing diagram during shutdown (RESET switches from HIGH to LOW)
Qn, QODTn,
Dn, DODTn,
CSGEN
DCKEn
PAR_IN
(1) After RESET is switched from HIGH to LOW, all data and clock input signals must be held at valid logic levels (not floating)
DCSn
QCKEn
RESET
QERR
CK
CK
for a minimum time of t
(1)
(1)
(1)
(1)
(1)
(1)
INACT(max)
.
RESET to Q
Rev. 02 — 2 March 2007
t
PHL
1.8 V DDR2-800 configurable registered buffer with parity
HIGH, LOW, or Don't care
t
INACT
t
RESET to QERR
PLH
HIGH or LOW
SSTUM32868
© NXP B.V. 2007. All rights reserved.
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