NAND08GAH0A NUMONYX [Numonyx B.V], NAND08GAH0A Datasheet - Page 29

• Manufacturer Part Number: NAND08GAH0A
• Manufacturer: NUMONYX [Numonyx B.V]

NAND08GAH0A, NAND16GAH0D
5.3.3
5.3.4
Table 11.
Start bit
0
Power class selection
After checking whether the NAND08GAH0A and NAND16GAH0D complies with
eMMC
the device power class.
After power-up or software reset (CMD0), the device defaults to operate in power class 0
which corresponds to the minimum current consumption for the card type (either Low or
High V
The PWR_CL_ff_vvv bytes of the EXT_CSD register report the power consumption levels of
the device, for a 4-bit or 8-bit bus width, at the supported clock frequencies (26 or 52 MHz).
The host can read the PWR_CL_ff_vvv bytes by issuing a SEND_EXT_CSD command, and
determine if it will allow the device to use a higher power class.
The power class can be changed by using the SWITCH command to program the
POWER_CLASS Byte, in the modes segment of the EXT_CSD register.
The valid values for the EXT_CSD register are defined in (see
PWR_CL_ff_vvv).
remains unchanged and the SWITCH_ERROR bit is set.
Bus test procedure
The host can detect the bus functional lines by issuing CMD19 and CMD14 commands.
The following steps are required to test the bus functional signals:
1.
2.
3.
The device has internal pull-up resistor on DAT1-DAT7 lines. If the device is connected to 1-
bit or 4-bit high-speed MMC system, the input value of the upper bits (e.g. DAT1-DAT7 or
DAT4-DAT7) are detected as logic “1” by the device.
Data format
The host must issue a CMD19 command, followed by a specific data pattern on each
selected data lines (see
include a CRC16 checksum, which is ignored by the device. The data pattern to be
sent per data line is defined in
width.
The host must then requests the device to send back the reversed data pattern. This is
done by issuing a CMD14 command. The device detects the start bit on DAT0 and
synchronizes accordingly the reading of all data inputs. It ignores all data pattern bits
except for the first two bits. The device buffer size consequently does not limit the
maximum length of the data pattern. The minimum length of the data pattern is two
bytes, of which the first two bits of each data line are sent back reversed by the device.
The host detects the bus functional lines by comparing the initial data pattern with the
reversed pattern sent back by the device. The host ignores all bits except for the first
two bits of the reversed data pattern. The length of the reversed data pattern is eight
bytes and is always sent using all the device DAT lines (see
Table
CRC16 checksum, which is ignored by the host.
™
CCQ
/MultiMediaCard system specification version 4.0 or higher, the host can change
14). The reversed data pattern sent by the device may optionally include a
voltage range).
If the value programmed by the host is invalid, the POWER_CLASS byte
1 0 x x x x ... x x
Data pattern
Table
11). The data pattern sent by the host may optionally
Table
12,
Table 13
High speed MultiMediaCard operation
and
Checksum
Table
CRC16
bit
Section 8.4.3:
14, according to the bus
Table
12,
Table 13
End bit
1
and
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