NAND08GAH0A NUMONYX [Numonyx B.V], NAND08GAH0A Datasheet - Page 72

• Manufacturer Part Number: NAND08GAH0A
• Manufacturer: NUMONYX [Numonyx B.V]

Device registers
8.5
8.6
8.7
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RCA (relative card address) register
The writable 16-bit relative card address (RCA) register carries the device address assigned
by the host during the device identification. This address is used for the addressed host-card
communication after the device identification procedure. The default value of the RCA
register is 0x0001. The value 0x0000 is reserved to set all cards into the Standby state with
CMD7.
DSR (driver stage register) register
The 16-bit driver stage register (DSR) can be optionally used to improve the bus
performance for extended operating conditions (depending on parameters like bus length,
transfer rate or number of devices on the bus).
The CSD register contains the information concerning the DSR register usage.
The default value of the DSR register is ‘0x404’.
Status register
The Status register provides information about the device current state and completion
codes for the last host command. The device status can be explicitly read (polled) with the
SEND_STATUS command. The MultiMediaCard Status register structure is defined in
Section 8.7: Status
Each of the Status register bit has three attributes:
●
●
Type
There are two types of Status register bits:
–
–
Detection mode
Exceptions can be detected by the device either during the command interpretation
and validation phase (Response mode) or during command execution phase
(Execution mode).
–
–
Error bit (E): it signals an error condition detected by the device. Error bits are
cleared as soon as the response reporting the error is sent back.
Status bit (S): it provides information on the device status and do not alter the
execution of the command being responded to. Status bits are non-volatile. They
are set and cleared according to the device status.
Response mode (R) exceptions are reported in the response to the command that
raised the exception. The command is not executed and the associated state
transition does not take place.
Execution mode (X) exceptions are reported in the response to a
STOP_TRANSMISSION command used to terminate the operation or in the
response to a GET_STATUS command issued while the operation is being carried
out or after the operation is completed. When an error is detected in X mode, the
error will be reported in the response to the next command. Note that
ADDRESS_OUT_OF_RANGE and ADDRESS_MISALIGN exceptions may be
detected both in Response and Execution modes. The conditions for each one of
the modes are explicitly defined in
register.
Table
59.
NAND08GAH0A, NAND16GAH0D