NAND08GAH0A NUMONYX [Numonyx B.V], NAND08GAH0A Datasheet - Page 79

• Manufacturer Part Number: NAND08GAH0A
• Manufacturer: NUMONYX [Numonyx B.V]

NAND08GAH0A, NAND16GAH0D
Figure 21. STOP_TRANSMISSION command timing diagram (CMD12, Data Transfer mode)
9.3
9.3.1
Figure 22. Single Block Write command timing diagram
Host Cmd
CMD
DAT0
DAT1-7
Data Write timings
Single Block Write
Before performing a data write operation, the host must select the device by issuing a CMD7
command, and set the valid block length for block oriented data transfer by issuing a CMD16
command.
The timing diagram for Single Block Write operation is given on
starts with a single block write command (CMD24) which determines the start address. The
data transfer from the host starts N
The data is suffixed with CRC check bits to allow the device to check it for transmission
errors. The device sends back the CRC check result as a CRC status token on the data line.
In the case of transmission error the device sends a negative CRC status (‘101’). In the case
of non erroneous transmission the device sends a positive CRC status (‘010’) and starts the
data programming procedure.
During the write operation, the device notifies the host that it is busy by holding DAT0 Low.
The data line goes High as soon as at least one receive buffer becomes free.
Z
Z
E Z
DAT
Z
Z
CMD
Z P * P S T
N
Cycles
* * * * * *
* * * * * *
CR
D D
S T
Host Command
D
Z
Z
Content
* * * * * * * *
Card Response
Z Z
Z Z
Content
* * *
* * *
CRC
CRC E
D
E
D
Z Z
Z Z
D
Z
Z
WR
N
Z
E
Z
P*P S
P*P S
WR
N
Cycles
P
Z
clock cycles after the device response was received.
P
CR
Z
* * *
* * * * * * * * * * * * * * * * *
Content
Content
* * * * * * * * * * * * * * * * * * *
Write Data
P
S
CRC
CRC
T
Card Response
Content
E
E
Z
Z
Z
Z
S
X
CRC
Figure
Status
CRC
Status
AI04329
P P
* * *
E
P P
E S L*L E
22. The sequence
Busy
P
P
X
P
Z
Z
P
Timings
AI13600
79/116