NAND08GAH0A NUMONYX [Numonyx B.V], NAND08GAH0A Datasheet - Page 34

• Manufacturer Part Number: NAND08GAH0A
• Manufacturer: NUMONYX [Numonyx B.V]

High speed MultiMediaCard operation
5.3.8
Note:
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If either one of the following errors is detected when the CMD17/CMD18 command is
received, the device rejects the CMD17/CMD18 command, remains in Transfer state and
sets the corresponding error bit:
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●
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If the device detects an error (e.g. address out of range, address misalignment, internal
error, etc.) during a Multiple Block Read operation, it stops data transmission and remains in
the sending data state (Data). The host must then abort the operation by sending the STOP-
TRANSMISSION command. The read error is reported in the response to the STOP-
TRANSMISSION command.
When the host uses partial blocks, if block misalignment is not allowed, the device returns a
block misalignment condition (ADDRESS_MISALIGN bit set to ‘1’) if the total length of the
partial blocks is not block aligned, and returns to Transfer state.
If the host sets the argument of the SET_BLOCK_COUNT command (CMD23) to 0, the
command is accepted; however, a subsequent read will follow the open-ended Multiple
Block Read protocol (STOP_TRANSMISSION command - CMD12 - is required).
Data Write
Data Writes allow data to be transferred from the host to the device. All data write
commands can be aborted any time by the CMD12 command. As soon as the data transfer
has completed, the device exits the Data Write state and switches either to the
Programming state (transfer successful) or Transfer state (transfer failed).
The Data Write format is similar to the Data Read format. For block oriented write data
transfer, the CRC check bits are added to each data block. The device performs a CRC
check for each data block received prior to a write operation. The polynomial is the same as
the one used for a read operation.
Read and Parameter Set commands are not allowed while the device is programming.
Moving another MultiMediaCard from Standby to Transfer state (using CMD7) does not
terminate a programming operation. The device switches to the Disconnect state and
releases the DAT line. The device can be reselected using CMD7. In this case it moves to
the Programming state and reactivates the busy indication.
The device provides buffering for Block Write. This means that the next block can be sent to
the device while the previous is being programmed. If all the write buffers are full, and the
device is in the Programming state, the DAT line will be kept Low.
There is no buffering option for Write CSD, Write CID and Erase. This means that while the
device is busy servicing any one of these commands, no other data transfer commands will
be accepted. The DAT line will be kept Low as long as the device is busy and in the
Programming state.
Care should be taken by the host not to reset a device (using CMD0 or CMD15) during any
pending or active programming operation. This will terminate the operation and may destroy
the data stored on the device.
The address provides by the host as an argument to either CMD17 or CMD18 is out of
range. ADDRESS_OUT_OF_RANGE is set.
The currently defined block length is illegal for a read operation. BLOCK_LEN_ERROR
is set.
The address/block-length combination positions the first data block is misaligned to the
device physical blocks. ADDRESS_MISALIGN is set.
NAND08GAH0A, NAND16GAH0D