HYB25D128160CE-5 QIMONDA [Qimonda AG], HYB25D128160CE-5 Datasheet - Page 16

• Manufacturer Part Number: HYB25D128160CE-5
• Description: 128-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1)
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (
Notes
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
Current State
Self Refresh
Self Refresh
Power Down
Power Down
All Banks Idle
All Banks Idle
Bank(s) Active
—
V
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
REF
must be maintained during Self Refresh operation
CKE n-1
Previous
Cycle
L
L
L
L
H
H
H
H
CKEn
Current
Cycle
L
H
L
H
L
L
L
H
Command n
X
Deselect or NOP
X
Deselect or NOP
Deselect or NOP
AUTO REFRESH
Deselect or NOP
See
Table 13
16
Action n
Maintain Self-Refresh
Exit Self-Refresh
Maintain Power-Down
Exit Power-Down
Precharge Power-Down Entry
Self Refresh Entry
Active Power-Down Entry
—
Truth Table 2: Clock Enable (CKE)
128-Mbit Double-Data-Rate SDRAM
HYB25D128xxxC[C/E/F/T](L)
t
XSNR
) period. A minimum of 200
Internet Data Sheet
TABLE 12
Note
1)
2)
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