HYB25D128160CE-5 QIMONDA [Qimonda AG], HYB25D128160CE-5 Datasheet - Page 29

• Manufacturer Part Number: HYB25D128160CE-5
• Description: 128-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1) 0 °C ≤
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) For each of the terms, if not already an integer, round to the next highest integer.
7)
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
Parameter
Data hold skew factor
Active to Autoprecharge delay
Active to Precharge command
Active to Active/Auto-refresh command period
Active to Read or Write delay
Average Periodic Refresh Interval
Auto-refresh to Active/Auto-refresh command period
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B command
Write preamble
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
other than CK/CK, is
t
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
between
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on
performance (bus turnaround) degrades accordingly.
HZ
and
T
t
A
LZ
V
≤ 70 °C
IH(ac)
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
and
; V
V
DDQ
V
IL(ac)
REF
= 2.5 V ± 0.2 V,
.
. CK/CK slew rate are ≥ 1.0 V/ns.
V
V
REF
t
DQSS
DD
stabilizes.
= +2.5 V ± 0.2 V (DDR333);
.
29
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
QHS
RAP
RAS
RC
RCD
REFI
RFC
RP
RPRE
RPST
RRD
WPRE
WPRES
WPST
WR
WTR
XSNR
XSRD
V
DDQ
–7
DDR266A
Min.
—
—
t
45
65
20
—
75
20
0.9
0.40
15
0.25
0
0.40
15
1
75
200
RCD
= 2.6 V ± 0.1 V,
t
CK
or
is equal to the actual system clock cycle time.
t
RASmin
128-Mbit Double-Data-Rate SDRAM
V
DD
Max.
+0.75
+0.75
—
120E+3
—
—
15.6
—
—
1.0
0.60
—
—
—
0.60
—
—
—
—
HYB25D128xxxC[C/E/F/T](L)
= +2.6 V ± 0.1 V (DDR400)
Unit Note
ns
ns
ns
ns
ns
ns
µs
ns
ns
t
t
ns
t
ns
t
ns
t
ns
t
CK
CK
CK
CK
CK
CK
Internet Data Sheet
Condition
TFBGA
TSOPII
—
—
—
—
10)
—
—
—
—
—
—
11)
12)
—
—
—
—
V
TT
1)
.
/ Test