HYB25D128160CE-5 QIMONDA [Qimonda AG], HYB25D128160CE-5 Datasheet - Page 27

• Manufacturer Part Number: HYB25D128160CE-5
• Description: 128-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1) 0 °C ≤
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) For each of the terms, if not already an integer, round to the next highest integer.
7)
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
Parameter
Data-out low-impedance time from
CK/CK
Mode register set command cycle
time
DQ/DQS output hold time
Data hold skew factor
Active to Autoprecharge delay
Active to Precharge command
Active to Active/Auto-refresh
command period
Active to Read or Write delay
Average Periodic Refresh Interval
Auto-refresh to Active/Auto-refresh
command period
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B
command
Write preamble
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command delay
Exit self-refresh to non-read
command
Exit self-refresh to read command
other than CK/CK, is
t
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
between
HZ
and
T
t
A
LZ
V
≤ 70 °C
IH(ac)
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
and
; V
V
DDQ
V
IL(ac)
REF
= 2.5 V ± 0.2 V,
.
. CK/CK slew rate are ≥ 1.0 V/ns.
V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
V
REF
LZ
MRD
QH
QHS
RAP
RAS
RC
RCD
REFI
RFC
RP
RPRE
RPST
RRD
WPRE
WPRES
WPST
WR
WTR
XSNR
XSRD
DD
stabilizes.
= +2.5 V ± 0.2 V (DDR333);
–5
DDR400B
Min.
–0.7
2
t
—
—
t
40
55
15
—
65
15
0.9
0.40
10
0.25
0
0.40
15
2
75
200
RCD
HP
–
t
QHS
27
Max.
+0.7
—
—
+0.50
+0.50
—
70E+3
—
—
15.6
—
—
1.1
0.60
—
—
—
0.60
—
—
—
—
V
DDQ
= 2.6 V ± 0.1 V,
–6
DDR333
Min.
–0.7
2
t
—
—
t
42
60
18
—
72
18
0.9
0.40
12
0.25
0
0.40
15
1
75
200
t
HP
RCD
CK
is equal to the actual system clock cycle time.
–
t
QHS
128-Mbit Double-Data-Rate SDRAM
V
DD
HYB25D128xxxC[C/E/F/T](L)
Max.
+0.7
—
—
+0.50
+0.55
—
70E+3
—
—
15.6
—
—
0.60
—
—
—
0.60
—
—
—
—
1.1
= +2.6 V ± 0.1 V (DDR400)
Unit Note
ns
t
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
t
t
ns
t
ns
t
ns
t
ns
t
CK
CK
CK
CK
CK
CK
CK
Internet Data Sheet
Condition
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—
—
TFBGA
TSOPII
—
—
—
—
10)
—
—
—
—
—
—
11)
12)
—
—
—
—
V
TT
.
1)
/ Test