HYB25D128160CE-5 QIMONDA [Qimonda AG], HYB25D128160CE-5 Datasheet - Page 26

• Manufacturer Part Number: HYB25D128160CE-5
• Description: 128-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

Rev. 1.6, 2007-02
03292006-U5AN-6TI1
Parameter
DQ output access time from CK/CK
CK high-level width
Clock cycle time
CK low-level width
Auto precharge write recovery +
precharge time
DQ and DM input hold time
DQ and DM input pulse width (each
input)
DQS output access time from CK/CK
DQS input low (high) pulse width
(write cycle)
DQS-DQ skew (DQS and associated
DQ signals)
DQS-DQ skew (DQS and associated
DQ signals)
Write command to 1
transition
DQ and DM input setup time
DQS falling edge hold time from CK
(write cycle)
DQS falling edge to CK setup time
(write cycle)
Clock Half Period
Data-out high-impedance time from
CK/CK
Address and control input hold time
Control and Addr. input pulse width
(each input)
Address and control input setup time
st
DQS latching
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CH
CK
CL
DAL
DH
DIPW
DQSCK
DQSL,H
DQSQ
DQSQ
DQSS
DS
DSH
DSS
HP
HZ
IH
IPW
IS
–5
DDR400B
Min.
–0.5
0.45
5
6
7.5
0.45
(
0.4
1.75
–0.5
0.35
—
—
0.72
0.4
0.2
0.2
min. (
—
0.6
0.7
2.2
0.6
0.7
t
WR
/
t
CK
t
CL
)+(
,
t
t
CH
26
RP
)
/
t
CK
Max.
+0.5
0.55
8
12
12
0.55
—
—
+0.5
—
+0.40
+0.40
1.25
—
—
—
—
+0.7
—
—
—
—
—
)
–6
DDR333
Min.
–0.7
0.45
6
6
7.5
0.45
(
0.45
1.75
–0.6
0.35
—
—
0.75
0.45
0.2
0.2
min. (
–0.7
0.75
0.8
2.2
0.75
0.8
t
WR
/
t
AC Timing - Absolute Specifications
CK
t
CL
)+(
,
128-Mbit Double-Data-Rate SDRAM
t
t
CH
RP
)
/
t
CK
HYB25D128xxxC[C/E/F/T](L)
Max.
+0.7
0.55
12
12
12
0.55
—
—
+0.6
—
+0.40
+0.45
1.25
—
—
—
—
+0.7
—
—
—
—
—
)
Unit Note
ns
t
ns
ns
ns
t
t
ns
ns
ns
t
ns
ns
t
ns
t
t
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
Internet Data Sheet
TABLE 22
Condition
2)3)4)5)
—
CL = 3.0
CL = 2.5
CL = 2.0
—
6)
—
—
—
—
TFBGA
TSOPII
—
—
—
—
—
7)
fast slew rate
8)
9)
fast slew rate
slow slew rate
slow slew rate
1)
/ Test