HYB25D128160CE-5 QIMONDA [Qimonda AG], HYB25D128160CE-5 Datasheet - Page 24

• Manufacturer Part Number: HYB25D128160CE-5
• Description: 128-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1)
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until
4)
5) The value of
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Closing Point Voltage, CK and CK Inputs
Parameter
Operating Current: one bank; active/ precharge;
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two
clock cycles.
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤
Precharge Floating Standby Current: CS ≥
CKE ≥
and DM.
Precharge Quiet Standby Current:CS ≥
inputs stable at ≥
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤
Active Standby Current: one bank active; CS ≥
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle.
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once
per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3
for DDR333;
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once
per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3
for DDR333;
Auto-Refresh Current:
Self-Refresh Current: CKE ≤ 0.2 V; external clock on;
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test
conditions.
V
V
DDQ
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
V
V
= 2.5 V ± 0.2 V,
IHMIN
ILMAX
;
t
t
;
t
CK
CK
V
CK
t
CK
IX
=
=
=
is expected to equal 0.5 ×
V
=
t
t
t
IHMIN
CKMIN
CKMIN
CKMIN
t
CKMIN
V
t
DD
RC
or ≤
;
, address and other control inputs changing once per clock cycle,
I
;
= +2.5 V ± 0.2 V (DDR200 - DDR333);
OUT
=
V
t
IN
V
RFCMIN
ILMAX
= 0 mA
=
V
REF
;
, burst refresh
V
IN
V
for DQ, DQS and DM.
REF
V
=
IHMIN
V
V
stabilizes.
DDQ
V
REF
IHMIN
, all banks idle; CKE ≥
of the transmitting device and must track variations in the DC level of the same.
V
for DQ, DQS and DM.
IHMIN
t
, all banks idle;
RC
=
; CKE ≥
t
t
RCMIN
CK
=
t
;
CKMIN
V
24
t
V
Symbol
V
V
V
V
DDQ
CK
IHMIN
IH(AC)
IL(AC)
ID(AC)
IX(AC)
=
= 2.6 V ± 0.1 V,
t
;
CKMIN
V
t
RC
IHMIN
=
;
Min.
V
—
0.7
0.5 ×
0.2
;
t
REF
RASMAX
t
CK
+ 0.31
V
=
DDQ
V
t
CKMIN
;
DD
t
CK
Values
= +2.6 V ± 0.1 V (DDR400); 0 °C ≤
128-Mbit Double-Data-Rate SDRAM
–
V
ILMAX
=
, address and other control
Max.
—
V
V
0.5 ×
0.2
t
CKMIN
REF
DDQ
V
;
IN
t
HYB25D128xxxC[C/E/F/T](L)
CK
– 0.31
=
+ 0.6
V
; DQ, DM and DQS
AC Operating Conditions
DDQ
V
=
REF
t
CKMIN
+
for DQ, DQS
Internet Data Sheet
Unit
V
V
V
V
I
TABLE 19
TABLE 20
DD
Note
Condition
2)3)
—
4)
5)
Conditions
Symbol
I
I
I
I
I
I
I
I
I
I
I
I
T
1)
DD0
DD1
DD2P
DD2F
DD2Q
DD3P
DD3N
DD4R
DD4W
DD5
DD6
DD7
A
/ Test
≤ 70 °C