HYB25D128160CE-5 QIMONDA [Qimonda AG], HYB25D128160CE-5 Datasheet - Page 18

• Manufacturer Part Number: HYB25D128160CE-5
• Description: 128-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those
3) Current state definitions: Idle: The bank has been precharged, and
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6) All states and sequences not shown are illegal or reserved.
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
8) Requires appropriate DM masking.
9) Concurrent Auto Precharge:This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto
10) A Write command may be applied after the completion of data output.
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
Current State
Any
Idle
Row Activating,
Active, or
Precharging
Read (Auto
Precharge
Disabled)
Write (Auto
Precharge
Disabled)
Read (With Auto
Precharge)
Write (With Auto
Precharge)
the previous state was self refresh).
allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in
the notes below.
and
Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, w. Auto Precharge disabled,
and has not yet terminated or been terminated. Read w. Auto Precharge Enabled: See
Auto Precharge disabled.
precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from
a read or write command with auto precharge enable, to a command to a different banks is summarized in
t
RCD
has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, w. Auto
CS
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS CAS WE
X
H
X
L
H
H
L
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
H
H
L
L
H
H
L
L
H
H
L
L
H
Truth Table 4: Current State Bank n - Command to Bank m (different bank)
X
H
X
H
H
L
L
H
H
L
H
H
L
L
H
H
L
L
H
H
L
L
Command
Deselect
No Operation
Any Command
Otherwise Allowed to
Bank m
Active
Read
Write
Precharge
Active
Read
Precharge
Active
Read
Write
Precharge
Active
Read
Write
Precharge
Active
Read
Write
Precharge
18
t
RP
Table
has been met. Row Active: A row in the bank has been activated,
12: Clock Enable (CKE) and after
Action
NOP. Continue previous operation.
NOP. Continue previous operation.
—
Select and activate row
Select column and start Read burst
Select column and start Write burst
—
Select and activate row
Select column and start new Read burst
—
Select and activate row
Select column and start Read burst
Select column and start new Write burst
—
Select and activate row
Select column and start new Read burst
Select column and start Write burst
—
Select and activate row
Select column and start Read burst
Select column and start new Write burst
—
10)
. Write w. Auto Precharge Enabled: See
128-Mbit Double-Data-Rate SDRAM
HYB25D128xxxC[C/E/F/T](L)
Table
t
XSNR
Internet Data Sheet
15.
/
t
XSRD
TABLE 14
has been met (if
1)2)3)4)5)6)
1) to 6)
1) to 6)
1) to 6)
1) to 7)
1) to 7)
1) to 6)
1) to 6)
1) to 7)
1) to 6)
1) to 6)
1) to 8)
1) to 7)
1) to 6)
1) to 6)
1) to 7), 9)
1) to 7), 10)
1) to 6)
1) to 6)
1) to 7)
1) to 7)
1) to 6)
Note
10)
.