HYB25D128160CE-5 QIMONDA [Qimonda AG], HYB25D128160CE-5 Datasheet - Page 3

• Manufacturer Part Number: HYB25D128160CE-5
• Description: 128-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1
This chapter contains features and the description.
1.1
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is center-aligned with data for writes
• Differential clock inputs
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: 2, 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• RAS-lockout supported
• 7.8 µs Maximum Average Periodic Refresh Interval
• 2.5 V (SSTL_2 compatible) I/O
•
•
• P(G)-TFBGA-60 package with 3 depopulated rows (8 × 12 mm
• P(G)-TSOPII-66 package
• Lead- and halogene-free = green product
Rev. 1.6, 2007-02
03292006-U5AN-6TI1
Part Number Speed Code
Speed Grade
max. Clock Frequency
V
V
DDQ
DD
= 2.5 V ± 0.2 V (DDR266A, DDR333);
= 2.5 V ± 0.2 V (DDR266A, DDR333);
Overview
Features
t
RAP
=
Component
Module
@CL3
@CL2.5
@CL2
t
RCD
V
f
f
f
V
CK3
CK2.5
CK2
DD
DDQ
= 2.6 V ± 0.1 V (DDR400)
= 2.6 V ± 0.1 V (DDR400)
–5
DDR400B
PC3200-3033
200
166
133
3
2
)
–6
DDR333
PC2700–2533
166
166
133
128-Mbit Double-Data-Rate SDRAM
HYB25D128xxxC[C/E/F/T](L)
–7
DDR266A
PC2100-2033
—
143
133
Internet Data Sheet
Performance
TABLE 1
—
—
Unit
MHz
MHz
MHz