PIC24FJ128GB MICROCHIP [Microchip Technology], PIC24FJ128GB Datasheet - Page 118

• Manufacturer Part Number: PIC24FJ128GB
• Description: 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
• Manufacturer: MICROCHIP [Microchip Technology]

PIC24FJ256GB110 FAMILY
7.5
Because of the timing requirements imposed by USB,
an internal clock of 48 MHz is required at all times while
the USB module is enabled. Since this is well beyond
the maximum CPU clock speed, a method is provided
to internally generate both the USB and system clocks
from a single oscillator source. PIC24FJ256GB110
family devices use the same clock structure as other
PIC24FJ devices, but include a two-branch PLL system
to generate the two clock signals.
The USB PLL block is shown in Figure 7-2. In this
system, the input from the primary oscillator is divided
down by a PLL prescaler to generate a 4 MHz output.
This is used to drive an on-chip 96 MHz PLL frequency
multiplier to drive the two clock branches. One branch
uses a fixed divide-by-2 frequency divider to generate
the 48 MHz USB clock. The other branch uses a fixed
divide-by-3 frequency divider and configurable PLL
prescaler/divider to generate a range of system clock
frequencies. The CPDIV bits select the system clock
speed; available clock options are listed in Table 7-2.
The USB PLL prescaler does not automatically sense
the incoming oscillator frequency. The user must man-
ually configure the PLL divider to generate the required
4 MHz output, using the PLLDIV2:PLLDIV0 Configura-
tion bits. This limits the choices for primary oscillator
frequency to a total of 8 possibilities, shown in
Table 7-3.
FIGURE 7-2:
DS39897B-page 116
(4 MHz or
8 MHz)
Input from
POSC
Input from
FRC
FNOSC2:FNOSC0
Oscillator Modes and USB
Operation
USB PLL BLOCK
PLLDIV2:PLLDIV0
÷ 12
÷ 10
÷ 6
÷ 5
÷ 4
÷ 3
÷ 2
÷ 1
111
110
101
100
011
010
001
000
4 MHz
Preliminary
96 MHz
PLL
TABLE 7-2:
TABLE 7-3:
Input Oscillator
Frequency
÷ 2
÷ 3
MCU Clock Division
48 MHz
40 MHz
24 MHz
20 MHz
16 MHz
12 MHz
(CPDIV1:CPDIV0)
8 MHz
4 MHz
None (00)
32 MHz
÷2 (01)
÷4 (10)
÷8 (11)
SYSTEM CLOCK OPTIONS
DURING USB OPERATION
VALID PRIMARY
OSCILLATOR
CONFIGURATIONS FOR USB
OPERATIONS
HSPLL, ECPLL,
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
Clock Mode
ECPLL
ECPLL
XTPLL
© 2008 Microchip Technology Inc.
÷ 8
÷ 4
÷ 2
÷ 1
CPDIV1:CPDIV0
11
10
01
00
Clock Frequency
Microcontroller
PLL Output
for System Clock
48 MHz Clock
for USB Module
32 MHz
16 MHz
8 MHz
4 MHz
PLL Division
(PLLDIV2:
PLLDIV0)
÷12 (111)
÷10 (110)
÷6 (101)
÷5 (100)
÷4 (011)
÷3 (010)
÷2 (001)
÷1 (000)