PIC24FJ128GB MICROCHIP [Microchip Technology], PIC24FJ128GB Datasheet - Page 159

• Manufacturer Part Number: PIC24FJ128GB
• Description: 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 12-1:
© 2008 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-10
bit 9-7
bit 6-5
bit 4
bit 3
bit 2-0
Note 1:
U-0
U-0
—
—
The ICx input must also be configured to an available RPn pin. For more information, see Section 9.4
“Peripheral Pin Select”.
Unimplemented: Read as ‘0’
ICSIDL: Input Capture x Module Stop in Idle Control bit
1 = Input capture module halts in CPU Idle mode
0 = Input capture module continues to operate in CPU Idle mode
ICTSEL2:ICTSEL0: Input Capture Timer Select bits
111 = System clock (F
110 = Reserved
101 = Reserved
100 = Timer1
011 = Timer5
010 = Timer4
001 = Timer2
000 = Timer3
Unimplemented: Read as ‘0’
ICI1:ICI0: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
ICOV: Input Capture x Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
ICBNE: Input Capture x Buffer Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
ICM2:ICM0: Input Capture Mode Select bits
111 = Interrupt mode: input capture functions as interrupt pin only when device is in Sleep or Idle mode
110 = Unused (module disabled)
101 = Prescaler Capture mode: capture on every 16th rising edge
100 = Prescaler Capture mode: capture on every 4th rising edge
011 = Simple Capture mode: capture on every rising edge
010 = Simple Capture mode: capture on every falling edge
001 = Edge Detect Capture mode: capture on every edge (rising and falling), ICI1:ICI0 bits do not
000 = Input capture module turned off
R/W-0
ICI1
U-0
—
ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
(rising edge detect only, all other control bits are not applicable)
control interrupt generation for this mode
W = Writable bit
‘1’ = Bit is set
ICSIDL
R/W-0
R/W-0
ICI0
OSC
/2)
ICTSEL2
PIC24FJ256GB110 FAMILY
R-0, HC
R/W-0
ICOV
Preliminary
(1)
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ICTSEL1
R-0, HC
ICBNE
R/W-0
ICTSEL0
ICM2
R/W-0
R/W-0
(1)
x = Bit is unknown
ICM1
R/W-0
U-0
—
(1)
DS39897B-page 157
ICM0
R/W-0
U-0
—
(1)
bit 8
bit 0