PIC24FJ128GB MICROCHIP [Microchip Technology], PIC24FJ128GB Datasheet - Page 167

• Manufacturer Part Number: PIC24FJ128GB
• Description: 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 13-1:
© 2008 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-10
bit 9-8
bit 7
bit 6-5
bit 4
bit 3
bit 2-0
Note 1:
ENFLT0
R/W-0
U-0
—
2:
The OCx output must also be configured to an available RPn pin. For more information, see Section 9.4
“Peripheral Pin Select”.
OCFA pin controls OC1-OC4 channels; OCFB pin controls the OC5-OC9 channels. OCxR and OCxRS
are double-buffered only in PWM modes.
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare x in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
OCTSEL2:OCTSEL0: Output Compare x Timer Select bits
111 = System Clock
110 = Reserved
101 = Reserved
100 = Timer1
011 = Timer5
010 = Timer4
001 = Timer3
000 = Timer2
Unimplemented: Read as ‘0’
ENFLT0: Fault 0 Input Enable bit
1 = Fault 0 input is enabled
0 = Fault 0 input is disabled
Unimplemented: Read as ‘0’
OCFLT0: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is only cleared by software
OCM2:OCM0: Output Compare x Mode Select bits
111 =
110 =
101 =
100 =
011 =
010 =
001 =
000 =
U-0
U-0
—
—
OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
Center-aligned PWM mode on OCx
Edge-aligned PWM Mode on OCx
Double Compare Continuous Pulse mode: Initialize OCx pin low, toggle OCx state
continuously on alternate matches of OCxR and OCxRS
Double Compare Single-Shot mode: Initialize OCx pin low, toggle OCx state on matches of
OCxR and OCxRS for one cycle
Single Compare Continuous Pulse mode: Compare events continuously toggle OCx pin
Single Compare Single-Shot mode: Initialize OCx pin high, compare event forces OCx pin low
Single Compare Single-Shot mode: Initialize OCx pin low, compare event forces OCx pin high
Output compare channel is disabled
W = Writable bit
‘1’ = Bit is set
OCSIDL
R/W-0
U-0
—
R/W-0, HCS
OCTSEL2
PIC24FJ256GB110 FAMILY
OCFLT0
R/W-0
Preliminary
(2)
HCS = Hardware Clearable/Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRIGMODE
(2)
OCTSEL1
R/W-0
R/W-0
(1)
OCTSEL0
OCM2
R/W-0
R/W-0
(1)
x = Bit is unknown
OCM1
R/W-0
U-0
—
(1)
DS39897B-page 165
OCM0
R/W-0
U-0
—
(1)
bit 8
bit 0