PIC24FJ128GB MICROCHIP [Microchip Technology], PIC24FJ128GB Datasheet - Page 230

• Manufacturer Part Number: PIC24FJ128GB
• Description: 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
• Manufacturer: MICROCHIP [Microchip Technology]

PIC24FJ256GB110 FAMILY
REGISTER 18-2:
DS39897B-page 228
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-13
bit 12-11
bit 10
bit 9-8
bit 7-6
bit 5-2
bit 1-0
Note 1:
WAITB1
R/W-0
BUSY
R-0
2:
(1)
WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.
A single-cycle delay is required between consecutive read and/or write operations.
BUSY: Busy bit (Master mode only)
1 = Port is busy (not useful when the processor stall is active)
0 = Port is not busy
IRQM1:IRQM0: Interrupt Request Mode bits
11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
10 = No interrupt generated, processor stall activated
01 = Interrupt generated at the end of the read/write cycle
00 = No interrupt generated
INCM1:INCM0: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrement ADDR<10:0> by 1 every read/write cycle
01 = Increment ADDR<10:0> by 1 every read/write cycle
00 = No increment or decrement of address
MODE16: 8/16-Bit Mode bit
1 = 16-bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers
0 = 8-bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer
MODE1:MODE0: Parallel Port Mode Select bits
11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10 = Master mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>)
WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits
11 = Data wait of 4 T
10 = Data wait of 3 T
01 = Data wait of 2 T
00 = Data wait of 1 T
WAITM3:WAITM0: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 T
...
0001 = Wait of additional 1 T
0000 = No additional wait cycles (operation forced into one T
WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits
11 = Wait of 4 T
10 = Wait of 3 T
01 = Wait of 2 T
00 = Wait of 1 T
WAITB0
IRQM1
R/W-0
R/W-0
or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)
PMMODE: PARALLEL PORT MODE REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
CY
CY
CY
CY
WAITM3
IRQM0
R/W-0
R/W-0
CY
CY
CY
CY
; multiplexed address phase of 4 T
; multiplexed address phase of 3 T
; multiplexed address phase of 2 T
; multiplexed address phase of 1 T
CY
CY
WAITM2
INCM1
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WAITM1
INCM0
R/W-0
R/W-0
CY
CY
CY
CY
MODE16
CY
WAITM0
R/W-0
R/W-0
)
(2)
(1)
© 2008 Microchip Technology Inc.
x = Bit is unknown
(1)
WAITE1
MODE1
R/W-0
R/W-0
(1)
WAITE0
MODE0
R/W-0
R/W-0
bit 8
bit 0
(1)