PIC24FJ128GB MICROCHIP [Microchip Technology], PIC24FJ128GB Datasheet - Page 189

• Manufacturer Part Number: PIC24FJ128GB
• Description: 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
• Manufacturer: MICROCHIP [Microchip Technology]

16.0
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules available
in the PIC24F device family. The UART is a full-duplex
asynchronous system that can communicate with
peripheral devices, such as personal computers, LIN,
RS-232 and RS-485 interfaces. The module also sup-
ports a hardware flow control option with the UxCTS and
UxRTS pins and also includes an IrDA
decoder.
The primary features of the UART module are:
• Full-Duplex, 8 or 9-Bit data transmission through
• Even, Odd or No Parity options (for 8-bit data)
• One or two Stop bits
• Hardware Flow Control option with UxCTS and
FIGURE 16-1:
© 2008 Microchip Technology Inc.
Note:
the UxTX and UxRX pins
UxRTS pins
Note:
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
”Section 21. UART” (DS39708).
The UART inputs and outputs must all be assigned to available RPn pins before use. Please see
Section 9.4 “Peripheral Pin Select” for more information.
Family
UART SIMPLIFIED BLOCK DIAGRAM
Hardware Flow Control
Baud Rate Generator
UARTx Transmitter
UARTx Receiver
Reference
IrDA
®
®
encoder and
Manual”,
PIC24FJ256GB110 FAMILY
Preliminary
• Fully Integrated Baud Rate Generator with 16-Bit
• Baud Rates Ranging from 1 Mbps to 15 bps at
• 4-Deep, First-In-First-Out (FIFO) Transmit Data
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-bit mode with Address Detect
• Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA Support
A simplified block diagram of the UART is shown in
Figure 16-1. The UART module consists of these key
important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
Prescaler
16 MIPS
Buffer
(9th bit = 1)
UxRTS/BCLKx
UxCTS
UxRX
UxTX
DS39897B-page 187