OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 21

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

6.4.2
This register configures the operation of the multi-purpose I/O pins ‘MIO[1:0]’ as follows.
DS-0028 Jul 05
Bits
29
30
31
Bits
1:0
3:2
4
5
31:6
OXFORD SEMICONDUCTOR LTD.
Multi-purpose I/O Configuration register ‘MIC’ (Offset 0x04)
Description
Reload configuration from EEPROM.
Writing a 1 to this bit re-loads the configuration from EEPROM. This bit is
self-clearing after an EEPROM read
Reserved
Reserved
Description
MIO0 Configuration Register
00 -> MIO0 is a non-inverting input pin
01 -> MIO0 is an inverting input pin
10 -> MIO0 is an output pin driving ‘0’
11 -> MIO0 is an output pin driving ‘1’
MIO1 Configuration Register
00 -> MIO1 is a non-inverting input pin
01 -> MIO1 is an inverting input pin
10 -> MIO1 is an output pin driving ‘0’
11 -> MIO1 is an output pin driving ‘1’
MIO0 Power Management Event (PME) Enable.
A value of ‘1’ enables the MIO0 pin to set the PME_Status bit in the
Power Management Register PMCSR of the selected function, and
hence assert the PME# pin if this option has been enabled. A value of ‘0’
prevents MIO0 from setting the PCI PME_Status bit.
This pin can affect function 0 or function 1, through the control defined in
the GIS (local configuration) register.
MIO1 Power Management Event (PME) Enable.
A value of ‘1’ enables the MIO1 pin to set the PME_Status bit in the
Power Management Register PMCSR of the selected function, and
hence assert the PME# pin if this option has been enabled. A value of ‘0’
prevents MIO1 from setting the PCI PME_Status bit.
This pin can affect function 0 or function 1, through the control defined in
the GIS (local configuration) register.
Reserved
External-Free Release
EEPROM
EEPROM
Read/Write
-
-
-
W
W
W
W
-
Read/Write
PCI
W
R
-
PCI
RW
RW
RW
RW
R
OX16PCI952
Reset
Reset
0000h
0
0
0
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00
00
0
0