OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 33

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

Note 10:
Offset values not listed in the table are reserved for future use and must not be used.
To read or write to any of the Indexed Controlled Registers use the following procedure:
Writing to ICR registers:
Ensure that the last value written to LCR was not 0xBF (reserved for 650 compatible register access value).
Write the desired offset to SPR (address 111b).
Write the desired value to ICR (address 101b).
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
Register
Name
NMR
MDM
PIDX
ACR
CPR
CSR
GDS
DMS
TCR
CKS
FCH
REV
RFC
CKA
TTL
RTL
FCL
ID1
ID2
ID3
The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the Indexed Control Registers via ICR.
Offset
SPR
0x0C
0x0D
0X0F
0X10
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0E
0x11
0x12
0x13
10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R
R
R
R
R
Unused
Unused
Unused
Unused
inactive
FCR[7]
Enable
Status
TxRdy
Bit 7
Addit-
Force
Tx 1x
Mode
ional
0
Unused
Table 12: Indexed Control Register Set
Indexed Control Register Set
inactive
Tx CLK
Enable
FCR[6]
RxRdy
Bit 6
Select
Force
Read
ICR
0
External-Free Release
5 Bit “integer” part of
Unused
clock prescaler
reset the UART (Except the CKS and CKA registers)
SChar 4
wakeup
Unused
BDOUT
on DTR
Trigger
Enable
disable
FCR[5]
Bit 5
9
Level
950
SIN
th
Automatic Flow Control Lower Trigger Level (0-127)
Automatic Flow Control Higher Trigger level (1-127)
Bit
Writing 0x00 to this register will
Hardwired revision byte (0x04)
Transmitter Interrupt Trigger Level (0-127)
Hardwired Port Index ( 0x00 )
Hardwired ID byte 1 (0xC9)
Receiver Interrupt Trigger Level (1-127)
Hardwired ID byte 1 (0x16)
Hardwired ID byte 1 (0x50)
SChar 3
Wakeup
Unused
DTR 1x
Modem
Disable
Tx CLK
FCR[4]
Bit 4
DTR definition and
9
th
Bit
Unused
control
SChar 2
Wakeup
Δ DCD
disable
FCR[3]
Bit 3
9
Rx 1x
Mode
th
Bit
SChar 1
RI edge
Control
Trailing
disable
FCR[2]
Enable
Bit 2
9
Invert
signal
4 Bit N-times clock
Auto
DSR
Flow
selection bits [3:0]
DTR
th
0
Bit
3 Bit “fractional” part of
clock prescaler
9
Wakeup
Disable
internal
tx clock
th
Δ DSR
disable
FCR[1]
TxRdy
Bit 1
status
Invert
-bit Int.
( R )
En.
Tx
Clock Sel[1:0]
OX16PCI952
Receiver
Wakeup
Disable
internal
rx clock
Enable
disable
FCR[0]
Δ CTS
RxRdy
Status
Bit 0
status
Invert
Good
9 Bit
Data
Page 33
( R )
Rx