OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 55

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

8.3
The parallel port registers are described below.
It is assumed that the upper block is placed 400h above the lower block.
Note 1 : These registers are only available in EPP mode.
Note 2 : Prefix ‘n’ denotes that a signal is inverted at the connector. Suffix ‘#’ denotes active-low signalling
The reset state of PDR, EPPA and EPPD1-4 is not determinable (i.e. 0xXX).
The reset value of DSR is ‘XXXXX111’.
DCR and ECR are reset to ‘0000XXXX’ and ‘00000001’ respectively.
8.3.1
PDR is located at offset 000h in the lower block. It is the
standard parallel port data register. Writing to this register
in mode 000 (SPP mode) will drive data onto the parallel
port data lines. In all the other modes, the drivers may be
tri-stated by setting the direction bit in the DCR. Reads
from this register return the actual logic values on the
parallel port data lines.
8.3.2
A data byte written to this address will be interpreted as an
address if bit(7) is set, otherwise an RLE count for the next
data byte. Count = bit(6:0) + 1.
DS-0028 Jul 05
(Other modes)
(EPP mode)
OXFORD SEMICONDUCTOR LTD.
EcpDFifo
Register
ecpAFifo
EPPD1
EPPD2
EPPD3
EPPD4
EPPA
CnfgA
CnfgB
Name
TFifo
PDR
DSR
DCR
ECR
-
Register Description
1
Parallel port data register ‘PDR’
ECP FIFO Address / RLE
1
1
1
1
Address
Offset
000h
000h
001h
001h
002h
003h
004h
005h
006h
007h
400h
400h
400h
401h
402h
403h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
-
nBUSY
nBUSY
Bit 7
0
0
SPP (Compatibility Mode) Registers
Table 25: Parallel port register set
Mode[2:0]
Upper Address Block (BAR1)
Lower Address Block (BAR0)
ACK#
ACK#
Bit 6
int
0
External-Free Release
Bit 5
DIR
PE
Configuration A Register – always 90h
PE
Parallel Port Data Register
ECP FIFO : Address / RLE
8.3.3
DSR is located at offset 001h in the lower block. It is a read
only register showing the current state of control signals
from the peripheral. Additionally in EPP mode, bit 0 is set
to ‘1’ when an operation times out (see section 8.1.3)
DSR[0]:
EPP mode only: Timeout
logic 0 ⇒ EPP Timer Timeout has not occurred.
logic 1 ⇒ EPP Timer Timeout has occurred (Reading this
bit clears it).
Other Parallel Port modes: Unused
This bit returns a ‘1’.
EPP Address Register
EPP Data 1 Register
EPP Data 2 Register
EPP Data 3 Register
EPP Data 4 Register
Bit 4
INT_EN
Must write ‘00001’
SLCT
SLCT
ECP Data FIFO
Test FIFO
Reserved
Device status register ‘DSR’
Bit 3
nSLIN#
ERR#
ERR#
‘000000’
Bit 2
INIT#
INT#
INT#
Bit 1
nAFD#
1
1
OX16PCI952
Bit 0
Timeout
nSTB#
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