OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 25

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

Note 4 :
6.5
Interrupts in PCI systems are level-sensitive and can be
shared. In the OX16PCI952, there are five sources of
interrupts - one from each UART channel, two from Multi-
Purpose IO pins (MIO0 to MIO1), and one from the parallel
port.
All interrupts can be routed to the PCI interrupt pins, INTA#
or INTB#. The default values assigned to the interrupt pin
field within each function’s PCI configuration space results
in all Function 0 interrupts to be made available on the
INTA# pin, and all Function1 interrupts also to be made
available on the INTA# pin (The interrupt pin fields are the
same).
These default interrupt pin values may be modified (for
example, to map function 1 interrupts on the INTB# line or
disable all interrupts altogether) by writing to the Interrupt
Pin field in each function’s PCI configuration Space using
the serial EEPROM facility. The Interrupt Pin field is
normally considered a hard-wired read-only value in PCI. It
indicates to system software which PCI interrupt pin (if any)
is used by a function. The interrupt pin may only be
modified using the serial EEPROM facility, and card
developers must not set any value which violates the PCI
local bus specification on this issue. If in doubt, the default
values should be used.
Table 7 relates the Interrupt Pin field to the device pin
used.
NOTE 1:
The OXPCI952 has only 2 interrupt pins : INTA# and INTB#. Interrupt Pin
values other than 1 or 2, will result in that function not being able to assert
an interrupt.
During the system initialisation process and PCI device
configuration, system-specific software reads the interrupt
pin field to determine which (if any) interrupt pin is used by
each function. It programmes the system interrupt router to
logically connect this PCI interrupt pin to a system-specific
interrupt vector (IRQ). It then writes this routing information
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
Interrupt Pin Field Value
PCI Interrupts
Powerdown behaviour of the MIO pins is different when associated with function 0 or function 1. See section “Power Management”.
Table 7: ‘Interrupt pin’ definition
3 to 255
0
1
2
1
Interrupt Pin used
Reserved
INTA#
INTB#
None
External-Free Release
to the Interrupt Line field in the function’s PCI configuration
space. Device driver software must then hook the interrupt
using the information in the Interrupt Line field.
The Interrupt status for all sources of interrupts are
available using the GIS register in the Local Configuration
Register set, which can be accessed using I/O or Memory
accesses from both logical functions. This facility enables
each function to snoop on interrupts asserted from the
other function regardless of the interrupt routing. This is
valid only when the device is operating in the dual-function
mode.
The 5 sources of interrupts on the OX16PCI952, can be
enabled/disabled individually using the options in the local
configuration register “GIS”.
By default, the interrupt options for the UARTs and the
parallel port are enabled in the GIS register. Following the
initial PCI configuration process, any UART based
interrupts that are generated as a result of 1
interrupts in the UART’s interrupt register (the ISR register)
will result in the assertion of the UART interrupt on the
interrupt pin of function 0. By the same token, any parallel
port based interrupts will result in the assertion of the
parallel port interrupt on the interrupt pin of function 1.
Once the interrupt options for the Multi-purpose MIO pins
(MIO0, MIO1) are enabled in the GIS register, the assertion
of these pins will, following the initial PCI configuration
process, assert an interrupt on the selected function’s
interrupt pin. The sense of the MIO pin (active-high or
active-low) that generates an interrupt is controlled by the
options in the MIC register.
For greater flexibility, the MIO pins can be individually
associated with either function0 or function1, thereby
affecting the selected functions interrupt, power-down, or
power management event logic.
Once an interrupt has been asserted, this interrupt can only
be removed by the device driver either by disabling the
relevant controls in the GIS register or by removing the
conditions on the 5 interrupt sources. For the UARTs, this
will require reads of the relevant register to clear any UART
based interrupts.
OX16PCI952
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enabling
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