AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 139
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AT83EC5123
Manufacturer Part Number
AT83EC5123
Description
(AT8xx512x) Smart Card Reader ICs
Manufacturer
ATMEL Corporation
Datasheet
1.AT83EC5123.pdf
(187 pages)
- Current page: 139 of 187
- Download datasheet (3Mb)
Watchdog Timer
Figure 85. Watchdog Timer
4202B–SCR–07/03
F
CK_WD
RESET
-
-
AT8xC5122 contains a powerfull programmable hardware Watchdog Timer (WDT) that
automatically resets the chip if its software fails to reset the WDT before the selected
time interval has elapsed. It permits large Timeout ranking from 16 ms to 2s @Fosc = 12
MHz.
This WDT consist of a 14-bit counter plus a 7 - bit programmable counter, a Watchdog
Timer reset register (WDTRST) and a Watchdog Timer programmation (WDTPRG) reg-
ister. When exiting reset, the WDT is -by default- disable. To enable the WDT, the user
has to write the sequence 1EH and E1H into WDRST register. When the Watchdog
Timer is enabled, it will increment every machine cycle while the oscillator is running
and there is no way to disable the WDT except through reset (either hardware reset or
WDT overflow reset). When WDT overflows, it will generate an output RESET pulse at
the RST pin. The RESET pulse duration is 96xT
best use of the WDT, it should be serviced in those sections of code that will periodically
be executed within the time required to prevent a WDT reset.
The WDT is controlled by two registers (WDTRST and WDTPRG).
-
WDTRST
WDTPRG
-
14-bit COUNTER
Enable
-
2
1
0
WR
Control
Decoder
7 - bit COUNTER
Outputs
OSC
, where T
AT8xC5122/23
OSC
=1/F
OSC
RESET
. To make the
139
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