AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 32

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

USB Clock
Oscillator
PLL
PLL Description
32
AT8xC5122/23
The USB Interface Block use two clock trees:
Two clock sources are available for CPU:
•
•
Figure 14. Crystal Connection
The AT8xC5122 PLL is used to generate internal high frequency clock synchronized
with an external low-frequency. Figure 15 shows the internal structure of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON
register is used to enable the clock generation. When the PLL is locked, the bit PLOCK
in PLLCON register is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PLLF pin (see
Figure 16). Value of the filter components are detailed in the Section “DC
Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage V
duced by the charge pump. It generates a square wave signal: the PLL clock.The
CK_PLL frequency is defined by the follwing formula:
F
CK_PLL
–
–
Crystal oscillator on XTAL1 and XTAL2 pins: Up to 8 MHz
External 48 MHz clock on XTAL1 pin
= F
The first one is the CPU clock used for the interface with the microcontroller,
CK_IDLE.
The second one is the USB clock, CK_USB. Since the USB frequency must
be
48 MHz, a 96 MHz PLL with a by 2 divider has to be used. An external
frequency can also be used.
CK_XTAL1
* (R+1) / (N+1)
8 MHz
XTAL1
XTAL2
4202B–SCR–07/03
REF
pro-