AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 141

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

Watchdog Timer During
Power-down Mode and
Idle
4202B–SCR–07/03
Table 105. Timeout value for Fosc = 12 MHz
Table 106. Watchdog Timer Enable register (Write Only) - WDTRST (A6h)
Reset Value = XXXX XXXXb
The WDTRST register is used to reset/enable the WDT by writing 1EH then E1H in
sequence.
In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode the user does not need to service the WDT. There are 2 methods of
exiting Power-down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power-down mode. When Power-down is exited with
hardware reset, servicing the WDT should occur as it normally does whenever
AT8xC5122 is reset. Exiting Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service for the interrupt used
to exit Power-down.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it
is best to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting
while in Idle mode, the user should always set up a timer that will periodically exit Idle,
service the WDT, and re-enter Idle mode.
7
-
S2
0
0
0
0
1
1
1
1
6
-
S1
0
0
1
1
0
0
1
1
5
-
S0
0
1
0
1
0
1
0
1
4
-
3
-
Timeout for F
2
AT8xC5122/23
-
131.07 ms
262.14 ms
524.29 ms
16.38 ms
32.77 ms
65.54 ms
1.05 s
2.10 s
CK_WD
= 6 MHz
1
-
0
-
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