AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 151

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

ASSEMBLY LANGUAGE
Registers
4202B–SCR–07/03
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a par-
ticular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value.
For example, the block move routine works the same whether DPS is ’0’ or ’1’ on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
See Table 108 on page 146 for the definition of AUXR register.
Table 111. Auxiliary Register 1 AUXR1- (0A2h) for AT8xC5122
Reset Value = XX1X XX0X0b (Not bit addressable)
Number
7 - 6
Bit
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ;increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
5
4
3
2
1
0
7
-
Mnemonic Description
AUXR1 QU 0A2H
ENBOOT
GF3
DPS
Bit
0
-
-
-
6
-
Reserved
The value read from this bit is indeterminate. Do not change these bits.
Enable Boot ROM (ROM/CRAM version only)
Set this bit to map the Boot ROM from 8000h to FFFFh. If the PC increments
beyond 7FFFh address, the code is fetch from internal ROM
Clear this bit to disable Boot ROM. If the PC increments beyond 7FFFh address,
the code is fetch from external code memory (C51 standard roll over function)
This bit is forced to 1 at reset
Reserved
The value read from this bit is indeterminate. Do not change this bit.
This bit is a general-purpose user flag.
Always cleared.
Reserved
The value read from this bit is indeterminate. Do not change this bit.
Data Pointer Selection
Cleared to select DPTR0. Set to select DPTR1.
ENBOOT
5
4
-
GF3
3
2
AT8xC5122/23
0
1
-
DPS
0
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