AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 31

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AT83EC5123

Manufacturer Part Number
AT83EC5123
Description
(AT8xx512x) Smart Card Reader ICs
Manufacturer
ATMEL Corporation
Datasheet
Smart Card Interface Block
Alternate Card Clock
DC/DC Clock
4202B–SCR–07/03
The Smart Card Interface Block (SCIB) uses two clock trees:
During SCI Reset, the CK_ISO input must be in the range 1 - 5 MHz according to ISO
7816. The SCIB clocks frequency is defined in Figure 27: Prescaler 2 Description and
Table 37 on page 43.
The alternate Card uses the peripheral clock divided by the PR3 prescaler. (1; 1/2; 1/4;
1/8 division ratio). See Section "Alternate Card", page 43 for the definition of the alter-
nate clock.
The DC/DC block needs a clock with a 50% duty cycle. The frequency must also respect
a value between 3.68 MHz and 6MHz. The PR4 prescaler is used to comply with the
DC/DC frequency requirement.
Figure 13. Functional Block Diagram
Before supplying the DC/DC block, the oscillator clock is adapted to the clock needed by
the DC/DC converter. This factor is controlled with the DCCKPS3:0 register.
Examples of factors are shown in the following table:
XTAL1 (MHz)
The first one, CK_IDLE, is the peripheral clock used for the interface with the
microcontroller.
The second one, CK_ISO, is independant from the CPU clock and is
generated from the PLL output. PR2, a 6-bit prescaler, will be used to
generate: 12/9.6/8/6.85/6/5.33/4.8/4.36/ ..../1MHz frequencies. SCIB clock
must be lower than CPU clock.
8
FCK_XTAL1
DCCKPS3:0 value
0
DCCKPS3:0
PR4
Prescaler
Factor
2
AT8xC5122/23
DC/DC converter CLK (MHz)
FCLK_DC/DC
4
31

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