AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 71
AT83EC5123
Manufacturer Part Number
AT83EC5123
Description
(AT8xx512x) Smart Card Reader ICs
Manufacturer
ATMEL Corporation
Datasheet
1.AT83EC5123.pdf
(187 pages)
- Current page: 71 of 187
- Download datasheet (3Mb)
Isochronous IN Transactions
in Standard Mode
Isochronous IN Transactions
in Ping-Pong Mode
4202B–SCR–07/03
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct.
An endpoint should be first enabled and configured before being able to send Isochro-
nous packets.
The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data stored in FIFO at the
next IN request concerning this endpoint.
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB
controller.
When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by
the USB controller. This triggers a USB interrupt if enabled. The firmware should clear
the TXCMPL bit before filling the endpoint FIFO with new data. The firmware should
never write more bytes than supported by the endpoint FIFO.
An endpoint should be first enabled and configured before being able to send Isochro-
nous packets.
The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit
in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at
the next IN request concerning the endpoint. The FIFO banks are automatically
switched, and the firmware can immediately write into the endpoint FIFO bank 1.
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB
controller.
When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the
USB controller. This triggers a USB interrupt if enabled. The firmware should clear the
TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are
then automatically switched.
When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the
USB controller. This triggers a USB interrupt if enabled. The firmware should clear the
TXCMPL bit before filling the endpoint FIFO bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by
the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,
the USB controller won’t send anything at each IN requests concerning this bank.
The firmware should never write more bytes than supported by the endpoint FIFO.
AT8xC5122/23
71
Related parts for AT83EC5123
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Monolithic Integrated Feature Phone Circuit
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Multistandard Video-IF and Quasi Parallel Sound Processing
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
High-performance EE PLD
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
8-bit Flash Microcontroller
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
2-Wire Serial EEPROM
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
U6046BREAR WINDOW HEATING TIMER / LONG-TERM TIMER
Manufacturer:
ATMEL Corporation
Datasheet: