AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 119

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

8
7
6
5
MFCOM
UINTCMD
UINT
RCVCCO
When MFCO is set, INTA is as-
serted if IENA is 1 and the mask
bit MFCOM is 0.
This bit is always read/write ac-
cessible. MFCO is cleared by the
host by writing a 1. Writing a 0
has no effect. MFCO is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
Mask. If MFCOM is set, the
MFCO bit will be masked and un-
able to set the INTR bit.
This bit is always read/write ac-
cessible. MFCOM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
UINTCMD can be used by the
host to generate an interrupt un-
related to any network activity.
When UINTCMD is set, INTA is
asserted if IENA is set to 1. Write
a 1 to UINT to clear UINTCMD
and stop interrupts.
This bit is always read/write ac-
cessible. UINTCMD is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
Am79C978 controller after the
host has issued a user interrupt
command by setting UINTCMD
(CSR4, bit 7) to 1.
This bit is always read/write ac-
cessible. UINT is cleared by the
host by writing a 1. Writing a 0
has no effect. UINT is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
flow is set by the Am79C978 con-
troller when the Receive Collision
Counter (CSR114 and CSR115)
has wrapped around.
When RCVCCO is set, INTA is
asserted if IENA is 1 and the
mask bit RCVCCOM is 0.
Missed Frame Counter Overflow
User
User Interrupt. UINT is set by the
Receive Collision Counter Over-
Interrupt
Command.
Am79C978
4
3
2
1-0
CSR5: Extended Control and Interrupt 1
Certain bits in CSR5 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR5 and write back
the value just read to clear the interrupt condition.
Bit
31-16 RES
RCVCCOM Receive Collision Counter Over-
TXSTRT
TXSTRTM
RES
Name
This bit is always read/write ac-
cessible. RCVCCO is cleared by
the host by writing a 1. Writing a
0 has no effect. RCVCCO is
cleared
S_RESET, or by setting the
STOP bit.
This bit is always read/write ac-
cessible. RCVCCOM is set to 1
by H_RESET or S_RESET and is
not affected by the STOP bit.
When TXSTRT is set, INTA is as-
serted if IENA is 1 and the mask
bit TXSTRTM is 0.
This bit is always read/write ac-
cessible. TXSTRT is cleared by
the host by writing a 1. Writing a
0 has no effect. TXSTRT is
cleared
S_RESET, or by setting the
STOP bit.
This bit is always read/write ac-
cessible. TXSTRTM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
flow Mask. If RCVCCOM is set,
the RCVCCO bit will be masked
and unable to set the INTR bit.
Am79C978 controller whenever it
begins transmission of a frame.
STRTM is set, the TXSTRT bit
will be masked and unable to set
the INTR bit.
zeros and read as undefined.
Description
zeros and read as undefined.
Transmit Start status is set by the
Transmit Start Mask. If TX-
Reserved locations. Written as
Reserved locations. Written as
by
by
H_RESET,
H_RESET,
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