AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 205

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

24
23
22-16 RES
15-12 ONES
11-00 BCNT
ENP
BPE
buffers. The STP bit must be set
in the first buffer of the frame, or
the Am79C978 controller will skip
over the descriptor and poll the
next descriptor(s) until the OWN
and STP bits are set. STP is set
by the host and is not changed by
the Am79C978 controller.
End of Packet. End of Packet in-
dicates that this is the last buffer
to be used by the Am79C978
controller for this frame. It is used
for data chaining buffers. If both
STP and ENP are set, the frame
fits into one buffer and there is no
data chaining. ENP is set by the
host and is not changed by the
Am79C978 controller.
Bus Parity Error is set by the
Am79C978 controller when a par-
ity error occurred on the bus inter-
face during a data transfers from
the transmit buffer associated
with
Am79C978 controller will only set
BPE when the advanced parity
error handling is enabled by set-
ting APERREN (BCR20, bit 10) to
1. BPE is set by the Am79C978
controller and cleared by the
host.
Reserved locations.
These four bits must be written as
ones. This field is written by the
host and unchanged by the
Am79C978 controller.
Buffer Byte Count is the usable
length of the buffer pointed to by
this descriptor, expressed as the
two’s complement of the length of
the buffer. This is the number of
bytes from this buffer that will be
transmitted by the Am79C978
controller. This field is written by
the host and is not changed by
This bit does not exist, when the
Am79C978 controller is pro-
grammed to use 16-bit software
structures for the descriptor ring
entries (BCR20, bits 7-0, SW-
STYLE is cleared to 0).
this
descriptor.
The
Am79C978
TMD2
Bit
31
30
29
BUFF
UFLO
EXDEF
Name
the Am79C978 controller. There
are no minimum buffer size re-
strictions.
Buffer
Am79C978
transmission
Am79C978 controller does not
find the ENP flag in the current
descriptor and does not own the
next descriptor. This can occur in
either of two ways:
1. The OWN bit of the next buffer
is 0.
2. FIFO underflow occurred be-
fore the Am79C978 controller ob-
tained
(TMD1[31:24]) of the next de-
scriptor. BUFF is set by the
Am79C978
cleared by the host.
If a Buffer Error occurs, an Un-
derflow Error will also occur.
BUFF is set by the Am79C978
controller and cleared by the
host.
Underflow error indicates that the
transmitter has truncated a mes-
sage because it could not read
data from memory fast enough.
UFLO indicates that the FIFO has
emptied before the end of the
frame was reached.
When DXSUFLO (CSR3, bit 6) is
cleared to 0, the transmitter is
turned off when an UFLO error
occurs (CSR0, TXON = 0).
When DXSUFLO is set to 1, the
Am79C978 controller gracefully
recovers from an UFLO error. It
scans the transmit descriptor ring
until it finds the start of a new
frame and starts a new transmis-
sion.
UFLO is set by the Am79C978
controller and cleared by the
host.
Excessive Deferral. Indicates that
the transmitter has experienced
Description
error
the
controller
is
controller
STATUS
when
set
by
during
byte
205
and
the
the