AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 30

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

controller during command portions of a read of the en-
tire EEPROM, or indirectly by the host system by read-
ing from BCR19, bit 0.
Note: The EEDO pin is multiplexed with the LED3 pin.
EESK
EEPROM Serial Clock
This pin is designed to directly interface to a serial
EEPROM that uses the 93C46 EEPROM interface pro-
tocol. EESK is connected to the EEPROM’s clock pin.
It is controlled by either the Am79C978 controller di-
rectly during a read of the entire EEPROM, or indirectly
by the host system by writing to BCR19, bit 1.
Note: The EESK pin is multiplexed with the LED1 pin.
The EESK pin is also used during EEPROM Auto-
Detection to determine whether or not an EEPROM is
present at the Am79C978 controller interface. At the
rising edge of the last CLK edge while RST is asserted,
EESK is sampled to determine the value of the EEDET
bit in BCR19. A sampled HIGH value means that an
EEPROM is present, and EEDET will be set to 1. A
sampled LOW value means that an EEPROM is not
present, and EEDET will be set to 0. See the EEPROM
Auto-Detection section for more details.
If no LED circuit is to be attached to this pin, then a pull-
up or pull-down resistor must be attached instead to re-
solve the EEDET setting.
WARNING: The input signal level of EESK must be
valid for correct EEPROM detection before the deas-
sertion of RST.
MII Interface
RX_CLK
Receive Clock
RX_CLK is a clock input that provides the timing refer-
ence for the transfer of the RX_DV, RXD[3:0], and
RX_ER signals into the Am79C978 device. RX_CLK
must provide a nibble rate clock (25% of the network
data rate). Hence, when the Am79C978 device is oper-
ating at 10 Mbps, it provides an RX_CLK frequency of
2.5 MHz, and at 100 Mbps it provides an RX_CLK fre-
quency of 25 MHz.
RXD[3:0]
Receive Data
RXD[3:0] is the nibble-wide MII-compatible receive
data bus. Data on RXD[3:0] is sampled on every rising
edge of RX_CLK while RX_DV is asserted. RXD[3:0] is
ignored while RX_DV is de-asserted.
RX_DV
Receive Data Valid
RX_DV is an input used to indicate that valid received
data is being presented on the RXD[3:0] pins and
30
Input
Input
Output
Input
Am79C978
RX_CLK is synchronous to the receive data. In order
for a frame to be fully received by the Am79C978 de-
vice, RX_DV must be asserted prior to the RX_CLK ris-
ing edge, when the first nibble of the Start of Frame
Delimiter is driven on RXD[3:0], and must remain as-
serted until after the rising edge of RX_CLK, when the
last nibble of the CRC is driven on RXD[3:0]. RX_DV
must then be deasserted prior to the RX_CLK rising
edge which follows this final nibble. RX_DV transitions
are synchronous to RX_CLK rising edges.
CRS
Receive Carrier Sense
CRS is an input that indicates that a non-idle medium,
due either to transmit or receive activity, has been de-
tected.
COL
Collision
COL is an input that indicates that a collision has been
detected on the network medium.
RX_ER
Receive Error
RX_ER is an input that indicates that the MII trans-
ceiver device has detected a coding error in the receive
data frame currently being transferred on the RXD[3:0]
pins. If RX_ER is asserted while RX_DV is asserted, a
CRC error will be indicated in the receive descriptor for
the incoming receive frame. RX_ER is ignored while
RX_DV is deasserted. Special code groups generated
on RXD while RX_DV is deasserted are ignored (e.g.,
bad SSD in TX and idle in T4). RX_ER transitions are
synchronous to RX_CLK.
TX_CLK
Transmit Clock
TX_CLK is a clock input that provides the timing refer-
ence for the transfer of the TXD[3:0] and TX_ER sig-
nals into the Am79C978 device. TX_CLK must provide
a nibble rate clock (25% of the network data rate).
Hence, when the Am79C978 device is operating at 10
Mbps, it provides an TX_CLK frequency of 2.5 MHz,
and at 100 Mbps it provides an RX_CLK frequency of
25 MHz.
TXD[3:0]
Transmit Data
TXD[3:0] is the nibble-wide MII-compatible transmit
data bus. Valid data is generated on TXD[3:0] on every
rising edge of TX_CLK while TX_EN is asserted. While
TX_EN is deasserted, TXD[3:0] values are driven to 0.
TXD[3:0] transitions are synchronous to rising edges of
TX_CLK.
Output
Input
Input
Input
Input