AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 36

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

The Auto-Poll’s frequency of generating MII manage-
ment frames can be adjusted by setting of the APDW
bits (BCR32, bits 10-8). The delay can be adjusted
from 0 MDC periods to 2048 MDC periods. Auto-Poll
by default will only read the MII Status register of the
currently active PHY.
Network Port Manager
If the PHY is active, the Network Port Manager will re-
quest status from the selected PHY by generating MII
management frames. These frames will be sent
roughly every 900 ms. These frames are necessary so
that the Network Port Manager can monitor the current
active link and can notify the software if the current link
goes down.
10BASE-T PHY
The 10BASE-T transceiver incorporates the physical
layer function, including both clock recovery (ENDEC)
and transceiver function. Data transmission over the
10BASE-T medium requires an integrated 10BASE-T
MAU. The transceiver will meet the electrical require-
ments for 10BASE-T as specified in IEEE 802.3i. The
transmit signal is filtered on the transceiver to reduce
harmonic content per IEEE 802.3i. Since filtering is
performed in silicon, external filtering modules are not
needed. The 10BASE-T PHY transceiver receives 10
Mbps data from the MAC across the internal MII at 2.5
million nibbles per second (parallel), or 10 million bits
per second (serial) for 10BASE-T. It then Manchester
encodes the data before transmission to the network.
The RX+ pins are differential twisted-pair receivers.
When properly terminated, each receiver will meet the
electrical requirements for 10BASE-T as specified in
IEEE 802.3i. Each receiver has internal filtering and
does not r equir e external fil ter modules. The
10BASE-T PHY transceiver receives a Manchester
coded 10BASE-T data stream from the medium. It then
recovers the clock and decodes the data. The data
stream is presented at the internal MII interface in par-
allel format.
PCI and JTAG Configuration Information
The PCI device ID and software configuration informa-
tion is as follows in Table 3 and Table 4.
36
Vendor ID
00001262h
1022
CSR89
Table 4. PCI Software Configuration
Table 3. PCI Device ID
Device ID
2001
00006003h
CSR88
Rev ID (offset 0x08)
1262 6003h
51
JTAG
Am79C978
Slave Bus Interface Unit
The slave Bus Interface Unit (BIU) controls all ac-
cesses to the PCI configuration space, the Control and
Status Registers (CSR), the Bus Configuration Regis-
ters (BCR), and the Address PROM (APROM) loca-
tions. Table 5 shows the response of the Am79C978
controller to each of the PCI commands in slave mode.
Slave Configuration Transfers
The host can access the PCI configuration space with
a c on f i g u r a t i o n r e a d o r w r i t e c o m m a n d . T h e
Am79C978 controller will assert DEVSEL during the
address phase when IDSEL is asserted, AD[1:0] are
both 0, and the access is a configuration cycle. AD[7:2]
select the DWord location in the configuration space.
The Am79C978 controller ignores AD[10:8], because it
C[3:0]
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
1011
1100
1101
0111
1110
1111
Interrupt
Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration
Read
Configuration
Write
Memory Read
Multiple
Dual Address
Cycle
Memory Read
Line
Memory Write
Invalidate
Table 5. Slave Commands
Command
Not used
Not used
Read of CSR, BCR, APROM,
and Reset registers
Write to CSR, BCR, and
APROM
Memory mapped I/O read of
CSR, BCR, APROM, and
Reset registers. Read of the
Expansion Bus
Memory mapped I/O write of
CSR, BCR, and APROM
Read of the Configuration
Space
Write to the Configuration
Space
Aliased to Memory Read
Not used
Aliased to Memory Read
Aliased to Memory Write
Use