AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 120

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

15
14
13-12
11
120
TOKINTD
LTINTEN
RES
SINT
TOKINTD is set to 1, the TINT bit
in CSR0 will not be set when a
transmission
Only a transmit error will set the
TINT bit.
TOKINTD has no effect when
LTINTEN (CSR5, bit 14) is set to
1. A transmit descriptor with
LTINT set to 1 will always cause
TINT to be set to 1, independent
of the success of the transmis-
sion.
This bit is always read/write ac-
cessible. TOKINTD is cleared by
H_RESET or S_RESET and is
unaffected by STOP.
When set to 1, the LTINTEN bit
will cause the Am79C978 control-
ler to read bit 28 of TMD1 as
LTINT. The setting LTINT will de-
termine if TINT will be set at the
end of the transmission.
This bit is always read/write ac-
cessible. LTINTEN is cleared by
H_RESET or S_RESET and is
unaffected by STOP.
zeros and read as undefined.
Am79C978 controller when it de-
tects a system error during a bus
master transfer on the PCI bus.
System errors are data parity er-
ror, master abort, or a target
abort. The setting of SINT due to
data parity error is not dependent
on the setting of PERREN (PCI
Command register, bit 6).
When SINT is set, INTA is assert-
ed if the enable bit SINTE is 1.
Note that the assertion of an in-
terrupt due to SINT is not depen-
dent on the state of the INEA bit,
since INEA is cleared by the
STOP reset generated by the
system error.
This bit is always read/write ac-
cessible. SINT is cleared by the
host by writing a 1. Writing a 0
Transmit OK Interrupt Disable. If
Last Transmit Interrupt Enable.
Reserved locations. Written as
System Interrupt is set by the
was
successful.
Am79C978
10
9-8
7
6
5
SINTE
RES
EXDINT
EXDINTE
MPPLBA
has no effect. The state of SINT is
not affected by clearing any of the
PCI Status register bits that get
set when a data parity error
(DATAPERR, bit 8), master abort
(RMABORT, bit 13), or target
abort (RTABORT, bit 12) occurs.
SINT is cleared by H_RESET or
S_RESET and is not affected by
setting the STOP bit.
This bit is always read/write ac-
cessible. SINTE is set to 0 by
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
When EXDINT is set, INTA is as-
serted if the enable bit EXDINTE
is 1.
This bit is always read/write ac-
cessible. EXDINT is cleared by
the host by writing a 1. Writing a
0 has no effect. EXDINT is
cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
This bit is always read/write ac-
cessible. EXDINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
System Interrupt Enable. If SIN-
TE is set, the SINT bit will be able
to set the INTR bit.
zeros and read as undefined.
Excessive Deferral Interrupt is
set by the Am79C978 controller
when the transmitter has experi-
enced Excessive Deferral on a
transmit frame, where Excessive
Deferral is defined in the ISO
8802-3 (IEEE/ANSI 802.3) stan-
dard.
Excessive Deferral Interrupt En-
able. If EXDINTE is set, the
EXDINT bit will be able to set the
INTR bit.
Broadcast Accept. If MPPLBA is
at its default value of 0, the
Reserved locations. Written as
Magic Packet Physical Logical