AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 127

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

CSR15: Mode
This register’s fields are loaded during the Am79C978
controller initialization routine with the corresponding
Initialization Block values, or when a direct register write
has been performed on this register.
Bit
31-16
15
14
13
12-9
8-7 PORTSEL[1:0] Port Select bits allow for software
Name
RES
PROM
DRCVBC
DRCVPA
RES
zeros and read as undefined.
PROM = 1, all incoming receive
frames are accepted.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
When
Am79C978 controller from re-
ceiving
Used for protocols that do not
support broadcast addressing,
except as a function of multicast.
DRCVBC is cleared by activation
of
(broadcast messages will be re-
ceived) and is unaffected by
STOP.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
dress. When set, the physical ad-
dress detection (Station or node
ID) of the Am79C978 controller
will be disabled. Frames ad-
dressed to the nodes individual
physical address will not be rec-
ognized.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
zeros and read as undefined.
controlled selection of the net-
work medium. The only legal val-
ues for this field is 11.
only when either the STOP or the
Description
Reserved locations. Written as
Promiscuous
Disable
Disable Receive Physical Ad-
Reserved locations. Written as
This bit is read/write accessible
H_RESET
broadcast
set,
Receive
Mode.
disables
or
messages.
Broadcast.
S_RESET
When
the
Am79C978
6
5
4
3
INTL
DRTY
FCOLL
DXMTFCS Disable Transmit CRC (FCS).
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
SPND bit is set. Cleared by
H_RESET or S_RESET and is
unaffected by STOP.
Internal Loopback. See the de-
scription of LOOP (CSR15, bit 2).
Disable Retry. When DRTY is set
to 1, the Am79C978 controller will
attempt only one transmission. In
this mode, the device will not pro-
tect the first 64 bytes of frame
data in the Transmit FIFO from
being overwritten, because auto-
matic retransmission will not be
necessary. When DRTY is set to
0, the Am79C978 controller will
attempt 16 transmissions before
signaling a retry error.
the collision logic to be tested.
The Am79C978 controller must
be in internal loopback for FCOLL
to be valid. If FCOLL = 1, a colli-
sion will be forced during loop-
back
which will result in a Retry Error.
If FCOLL = 0, the Force Collision
logic will be disabled. FCOLL is
defined after the initialization
block is read.
When DXMTFCS is set to 0, the
transmitter will generate and ap-
pend an FCS to the transmitted
frame. When DXMTFCS is set to
1, no FCS is generated or sent
with
DXMTFCS is overridden when
ADD_FCS and ENP bits are set
in TMD1.
bit11) is set to 1, the setting of
DXMTFCS has no effect.
Force Collision. This bit allows
When the APAD_XMT bit (CSR4,
the
transmission
transmitted
attempts,
frame.
127