AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 161

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

1
0
RST Pin
EEDET Value
(BCR19[13])
High
High
High
Low
ESK
EDI/EDO
0
0
1
1
Read in Progress
PREAD or Auto
Connected?
EEPROM Serial Clock. This bit
and the EDI/EDO bit are used to
control host access to the EE-
PROM. Values programmed to
this bit are placed onto the EESK
pin at the rising edge of the next
clock following bit programming,
except when the PREAD bit is set
to 1 or the EEN bit is set to 0. If
both the ESK bit and the EDI/
EDO bit values are changed dur-
ing one BCR19 write operation,
while EEN = 1, then setup and
hold times of the EEDI pin value
with respect to the EESK signal
edge are not guaranteed.
ESK has no effect on the EESK
pin unless the PREAD bit is set to
0 and the EEN bit is set to 1.
This bit is read accessible al-
ways, write accessible only when
either the STOP or the SPND bit
is set. ESK is reset to 1 by
H_RESET and is not affected by
S_RESET or STOP.
Data Out. Data that is written to
EEPROM
EEPROM
X
1
0
0
Yes
Yes
No
No
Data
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
Table 39. Interface Pin Assignment
Result if PREAD is Set to 1
EEN
In/EEPROM
X
X
1
0
Table 38. EEDET Setting
Am79C978
Bit of BCR19
From ECS
BCR20: Software Style
This register is an alias of the location CSR58. Accesses
to and from this register are equivalent to accesses to
CSR58.
Bit
31-11 RES
EECS
Active
0
0
Name
First two EESK clock cycles are generated,
then EEPROM read operation is aborted
and PVALID is reset to 0.
First two EESK clock cycles are generated,
then EEPROM read operation is aborted
and PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
From ESK Bit of
Result of Automatic EEPROM Read
Operation Following H_RESET
Tri-State
BCR19
EESK
Active
LED1
this bit will appear on the EEDI
output of the interface, except
when the PREAD bit is set to 1 or
the EEN bit is set to 0. Data that
is read from this bit reflects the
value of the EEDO input of the in-
terface.
EDI/EDO has no effect on the
EEDI pin unless the PREAD bit is
set to 0 and the EEN bit is set to
1.
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set. EDI/
EDO is reset to 0 by H_RESET
and is not affected by S_RESET
or STOP.
Reserved locations. Written as
zeros and read as undefined.
Description
From EEDI Bit of
Tri-State
BCR19
Active
LED0
EEDI
161