AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 169

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

13-12 FMDC
11
FMDC
00
01
10
11
APEP
Table 44. FMDC Values
Fast Management Data Clock
MII port. When the Auto Select bit
(ASEL, BCR2, bit 1) is a 1 and the
MIIPD bit is a 1, the MII port is se-
lected. Any transition on the MI-
IPD bit will set the MIIPDTI bit in
CSR7, bit 3.
Fast Management Data Clock (is
used for manufacturing tests).
When FMDC is set to 1h, the MII
Management Data Clock will run
at 5 MHz max. The Management
Data Clock will no longer be IEEE
802.3u-compliant and setting this
bit should be used with care. The
accompanying
must also be able to accept man-
agement frames at the new clock
rate. When FMDC is set to 0h, the
MII Management Data Clock will
run at 2.5 MHz max and will be
fully compliant to IEEE 802.3u
standards. See Table 44.
Auto-Poll PHY. When APEP is
set to 1 the Am79C978 controller
will poll the status register in the
PHY. This feature allows the soft-
ware driver or upper layers to see
any changes in the status of the
PHY. An interrupt when enabled
is generated when the contents of
the new status is different from
the previous status.
Read accessible always. MIIPD
is read only. Write operations are
ignored and should not be per-
formed.
This bit is always read/write ac-
cessible. FMDC is set to 0 during
H_RESET, and is unaffected by
S_RESET and the STOP bit
This bit is always read/write ac-
cessible. APEP is set to 0 during
H_RESET and is unaffected by
S_RESET and the STOP bit.
2.5 MHz max
5 MHz max
Reserved
Reserved
external
PHY
Am79C978
10-8
7
6
110-111
APDW
000
001
010
100
101
011
APDW
DANAS
XPHYRST
Continuous (26 s @ 2.5 MHz)
Every 128 MDC cycles (103 s @ 2.5 MHz)
Every 256 MDC cycles (206 s @ 2.5 MHz)
Every 512 MDC cycles (410 s @ 2.5 MHz)
Every 1024 MDC cycles (819 s @ 2.5 MHz)
Every 2048 MDC cycles (1640 s @ 2.5 MHz)
Reserved
Table 45. APDW Values
Auto-Poll Dwell Time. APDW de-
termines the dwell time between
PHY
accesses
turned on. See Table 45.
This bit is always read/write ac-
cessible. APDW is set to 100h af-
ter H_RESET and is unaffected
by S_RESET and the STOP bit.
Disable Auto-Negotiation Auto
Setup. When DANAS is set, the
Am79C978 controller after a
H_RESET or S_RESET will re-
main dormant and not automati-
cally startup the Auto-Negotiation
section or the enhanced automat-
ic port selection section. Instead,
the Am79C978 controller will wait
for the software driver to setup
the Auto-Negotiation portions of
the device. The PHY Address
and Data programming in BCR33
and BCR34 is still valid. The
Am79C978 controller will not
generate
frames unless Auto-Poll is en-
abled.
This bit is always read/write ac-
cessible. DANAS is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
PHY Reset. When XPHYRST is
set, the Am79C978 controller af-
ter an H_RESET or S_RESET
will issue management frames
that will reset the PHY. This bit is
needed when there is no way to
guarantee the state of the exter-
nal PHY. This bit must be repro-
grammed after every H_RESET.
Auto-Poll
Management
Dwell Time
when
any
Auto-Poll
management
Frame
169
is