AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 141

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

CSR88: Chip ID Register Lower
Bit
31-28 VER
27-12 PARTID
11-1
0
MANFID
ONE
Name
DMABC register is undefined un-
til written.
Version. This 4-bit pattern is
silicon-revision dependent.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. Write opera-
tions are ignored.
Part number. The 16-bit code for
the
0010 0110 0010 0110 (2626h).
Manufacturer ID. The 11-bit man-
ufacturer
00000000001b. This code is per
the JEDEC Publication 106-A.
Always a logic 1.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
This register is exactly the same
as the Device ID register in the
JTAG description. However, this
part number is different from that
stored in the Device ID register in
the PCI configuration space.
Read accessible only when either
the STOP or the SPND bit is set.
PARTID is read only. Write oper-
ations are ignored.
Note that this code is not the
same as the Vendor ID in the PCI
configuration space.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. MANFID is
read only. Write operations are
ignored.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. ONE is read
only. Write operations are ig-
nored.
Description
Am79C978
code
for
controller
AMD
Am79C978
is
is
CSR89: Chip ID Register Upper
Bit
31-16 RES
15-12 VER
11-0
CSR92: Ring Length Conversion
Bit
31-16 RES
15-0
CSR100: Bus Timeout
Bit
31-16 RES
15-0
PARTIDU
RCON
MERRTO
Name
Name
Name
This register contains the value of
Reserved locations. Read as un-
defined.
Version. This 4-bit pattern is
silicon-revision dependent.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. Write opera-
tions are ignored.
Upper 12 bits of the Am79C978
controller part number, i.e., 0010
0110 0010b (262h).
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. PARTIDU is
read only. Write operations are
ignored.
Reserved locations. Written as
zeros and read as undefined.
Ring Length Conversion Regis-
ter. This register performs a ring
length conversion from an encod-
ed value as found in the initializa-
tion block to a two’s complement
value used for internal counting.
By writing bits 15-12 with an en-
coded ring length, a two’s com-
plemented value is read. The
RCON register is undefined until
written.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Written as
zeros and read as undefined.
the longest allowable bus latency
(interval between assertion of
REQ and assertion of GNT) that a
Description
Description
Description
141