K9F2808Q0C-HCB0 SAMSUNG [Samsung semiconductor], K9F2808Q0C-HCB0 Datasheet
K9F2808Q0C-HCB0
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K9F2808Q0C-HCB0 Summary of contents
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... Add the data protection Vcc guidence for 1.8V device - below about 1.1V. (Page 33) 2.1 The min. Vcc value 1.8V devices is changed. K9F28XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V Pb-free Package is added. 2.2 K9F2808U0C-FCB0,FIB0 K9F2808Q0C-HCB0,HIB0 K9F2816U0C-HCB0,HIB0 K9F2816U0C-PCB0,PIB0 K9F2816Q0C-HCB0,HIB0 K9F2808U0C-HCB0,HIB0 K9F2808U0C-PCB0,PIB0 Some AC parameters are changed(K9F28XXQ0C). 2.3 tWC tWH tWP tRC tREH tRP tREA tCEA ...
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... Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you ...
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K9F2808U0C 16M x 8 Bit NAND Flash Memory PRODUCT LIST Part Number Vcc Range K9F2808U0C-Y,P 2.7 ~ 3.6V K9F2808U0C-V,F FEATURES • Voltage Supply : 2.7 ~ 3.6 V • Organization - Memory Cell Array -(16M + 512K)bit x 8bit - ...
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K9F2808U0C PIN CONFIGURATION (TSOP1) K9F2808U0C-YCB0,PCB0/YIB0,PIB0 N.C 1 N.C 2 N.C 3 N.C 4 N.C 5 GND 6 R N.C 10 N.C 11 Vcc 12 Vss 13 N.C 14 N.C 15 CLE 16 ALE 17 WE ...
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K9F2808U0C PIN CONFIGURATION (WSOP1) K9F2808U0C-VCB0,FCB0/VIB0,FIB0 N.C 1 N.C 2 DNU 3 N.C 4 N.C 5 N DNU 10 N.C 11 Vcc 12 Vss 13 N.C 14 DNU 15 CLE 16 ALE 17 WE ...
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K9F2808U0C PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The pins float to high-z when the chip ...
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K9F2808U0C Figure 1-1. K9F2808U0C FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE ...
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K9F2808U0C PRODUCT INTRODUCTION The K9F2808U0C is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare eight columns are located from column address of 512~527. A 528-byte data register is connected to memory cell arrays accommodating data transfer ...
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K9F2808U0C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F2808U0C-XCB0 Temperature Under Bias K9F2808U0C-XIB0 K9F2808U0C-XCB0 Storage Temperature K9F2808U0C-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level ...
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K9F2808U0C VALID BLOCK Parameter Symbol Valid Block Number N NOTE : device 1. The may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre- sented with both cases ...
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K9F2808U0C AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write ...
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K9F2808U0C NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block( called ...
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K9F2808U0C NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should ...
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K9F2808U0C NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I ...
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K9F2808U0C Pointer Operation of K9F2808U0C Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ...
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K9F2808U0C System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system ...
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K9F2808U0C Device K9F2808U0C Command Latch Cycle CLE t CLS ALS ALE I/Ox Address Latch Cycle t CLS CLE ALS ALE I/Ox I/O I/ CLH ...
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K9F2808U0C Input Data Latch Cycle CLE ALS WC ALE I/Ox DIN 0 Serial access Cycle after Read CE t REA RE I/ R/B NOTES : Transition is measured ±200mV from ...
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K9F2808U0C Status Read Cycle CLE t CLS I/Ox READ1 OPERATION (READ ONE PAGE) CLE ALE RE N Address Read I/Ox A9~A16 A0~A7 CMD Column Page(Row) Address Address R 528 , ...
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K9F2808U0C READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE RE N Address Read I/Ox Col. Add Row Add1 CMD Page(Row) Column Address Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE I/Ox 50h Col. Add Row ...
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K9F2808U0C SEQUENTIAL ROW READ OPERATION (only for K9F2808U0C-Y,P and K9F2808U0C-V,F valid wihin a block) CLE CE WE ALE RE 00h I/Ox Col. Add Row Add1 Row Add2 R/B M PAGE PROGRAM OPERATION CLE ALE RE N ...
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K9F2808U0C BLOCK ERASE OPERATION (ERASE ONE BLOCK) CLE ALE RE I/Ox 60h A9~A16 A17~A23 Page(Row) Address R/B Auto Block Erase Setup Command t t BERS WB DOh Busy Erase Command 22 FLASH MEMORY 70h I/O 0 ...
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K9F2808U0C MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I/Ox 90h Read ID Command Address. 1cycle REA 00h ECh Maker Code Device K9F2808U0C 23 FLASH MEMORY Device Code* Device Code Device Code* 73h ...
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K9F2808U0C DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis- ter along with three address cycles. Once the command is latched, it ...
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K9F2808U0C Figure 9. Read2 Operation CLE CE WE ALE R/B RE I/Ox Start Add.(3Cycle) 50h & A23 Don’t care 4 7 Figure 8-1. Sequential Row Read1 Operation R/B I/Ox ...
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K9F2808U0C Figure 9-1. Sequential Row Read2 Operation R/B I/Ox Start Add.(3Cycle) 50h & A23 ′ Don t Care) (GND Input=Fixed Low Data ...
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K9F2808U0C PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive bytes/words up to 528 single page program cycle. The number of consecutive partial ...
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K9F2808U0C BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com- mand(60h). Only address valid while loading initiates ...
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K9F2808U0C READ ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command ...
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K9F2808U0C READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase ...
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K9F2808U0C Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is ...