K9F2808Q0C-HCB0 SAMSUNG [Samsung semiconductor], K9F2808Q0C-HCB0 Datasheet - Page 24

• Manufacturer Part Number: K9F2808Q0C-HCB0
• Description: 16M x 8 Bit NAND Flash Memory
• Manufacturer: SAMSUNG [Samsung semiconductor]

K9F2808U0C
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred
to the data registers in less than 10µs(t
output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing
RE. High to low transitions of the RE clock output the data starting from the selected column address up to the last column
address[column 511/ 527 depending on the state of GND input pin].
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512
~527 bytes may be selectively accessed by writing the Read2 command with GND input pin low. Addresses A
address of the spare area while addresses A
area. Figures 8, 9 show typical sequence and timings for each read operation.
Sequential Row Read is available :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10µs
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of
a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 8-1, 9-1 show typical sequence and timings for sequential row read
operation.
Figure 8. Read1 Operation
NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
CLE
CE
WE
ALE
R/B
RE
I/Ox
array (00h) at next cycle.
00h
Start Add.(3Cycle)
A
0
~ A
7
& A
9
~ A23
R
). The system controller can detect the completion of this data transfer(tR) by analyzing the
4
~A
7
are ignored. The Read1 command is needed to move the pointer back to the main
t
R
(00h Command)
Data Field
Main array
CE must be held
low during tR
24
Spare Field
Data Output(Sequential)
1)
1st half array
FLASH MEMORY
(01h Command)
Data Field
2st half array
0~
A
3
Spare Field
set the starting