DM9161EP DAVICOM [Davicom Semiconductor, Inc.], DM9161EP Datasheet - Page 14

• Manufacturer Part Number: DM9161EP
• Description: 10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

MII Interface (continued)
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•
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14
TXD
CRS
CRS
TXD
TXER
synchronously with respect to TXCLK. If TXER is
asserted for one or more clock periods, and TXEN is
asserted, the PHY will emit one or more symbols that
are not part of the valid data delimiter set somewhere in
the frame being transmitted.
RXD (receive data) is a nibble (4 bits) of data that are
sampled by the reconciliation sublayer synchronously
with respect to RXCLK. For each RXCLK period which
RXDV is asserted, RXD (3:0) are transferred from the
PHY to the MAC reconciliation sublayer.
RXCLK (receive clock) output to the MAC reconciliation
sublayer is a continuous clock that provides the timing
reference for the transfer of the RXDV, RXD, and
RXER signals.
(transmit
IDLE
coding
10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver
SSD
error)
J/K
Preamble
Preamble
transitions
SFD
SFD
are
100Base-TX
Figure 7-2
10Base-T
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•
•
Data
RXDV (receive data valid) input from the PHY indicates
that the PHY is presenting recovered and decoded
nibbles to the MAC reconciliation sublayer. To interpret
a receive frame correctly by the reconciliation sublayer,
RXDV must encompass the frame, starting no later
than the Start-of-Frame delimiter and excluding any
End-Stream delimiter.
RXER (receive error) transitions are synchronously with
respect to RXCLK. RXER will be asserted for one or
more clock periods to indicate to the reconciliation
sublayer that an error was detected somewhere in the
frame being transmitted from the PHY to the
reconciliation sublayer.
CRS (carrier sense) is asserted by the PHY when either
the transmit or receive medium is non-idle, and
de-asserted by the PHY when the transmit and receive
medium are idle. Figure 7-2 depicts the behavior of
CRS during 10Base-T and 100Base-TX transmission.
Data
EFD
ESD
T/R
Version: DM9161-DS-F05
IDLE
DM9161
September 10, 2008
Final