DM9161EP DAVICOM [Davicom Semiconductor, Inc.], DM9161EP Datasheet - Page 31

• Manufacturer Part Number: DM9161EP
• Description: 10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

8.10 10BASE-T Configuration/Status (10BTCSR) - 18
8.11 DAVICOM Specified Interrupt Register – 21
Final
Version: DM9161-DS-F05
September 10, 2008
18.9-18.1
21.14-21.
18.15
18.14
18.13
18.12
18.11
18.10
21.15
21.11
21.10
18.0
21.9
21.8
Bit
Bit
12
INTR PEND
10BT_SER
INTR mask
SQUELCH
LINK mask
SPD mask
FDX mask
Bit Name
Reserved
Reserved
Bit Name
Reserved
LP_EN
JABEN
POLR
HBE
10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver
Default
Default
1, RW
1, RW
1, RW
0, RO
0, RO
1, RW
1, RW
1, RW
1, RW
0, RO
0, RO
1,RW
0, RO
0,RW
Reserved
Read as 0, ignore on write
Link Pulse Enable
1 = Transmission of link pulses enabled
0 = Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation
Heartbeat Enable
1 = Heartbeat function enabled
0 = Heartbeat function disabled
When the DM9161 is configured for full duplex operation, this bit will
be ignored (the collision/heartbeat function is invalid in full duplex
mode)
Squelch Enable
1 = Normal squelch
0 = Low squelch
Jabber Enable
Enables or disables the Jabber function when the DM9161 is in
10BASE-T full duplex or 10BASE-T transceiver loopback mode
1 = Jabber function enabled
0 = Jabber function disabled
10BASE-T GPSI Mode
1 = 10BASE-T GPSI mode selected
0 = 10BASE-T MII mode selected
GPSI mode is not supported for 100Mbps operation
Reserved
Read as 0, ignore on write
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable polarity is
reversed. This bit is automatically set and cleared by 10BASE-T
module
Interrupt Pending
Indicates that the interrupt is pending and is cleared by the current
read. This bit shows the same result as bit 0. (INTR Status)
Reserved
Full-duplex Interrupt Mask
When this bit is set, the Duplex status change will not generate the
interrupt
Speed Interrupt Mask
When this bit is set, the Speed status change will not generate the
interrupt
Link Interrupt Mask
When this bit is set, the link status change will not generate the
interrupt
Master Interrupt Mask
Description
Description
DM9161
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