DM9161EP DAVICOM [Davicom Semiconductor, Inc.], DM9161EP Datasheet - Page 22

• Manufacturer Part Number: DM9161EP
• Description: 10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

ADD
00
01
02
03
04
05
06
16
17
18
21
22
23
24
8. MII Register Description
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where：
<Reset Value>:
22
Disconnect
CONTROL
Expansion
Auto-Neg.
Auto-Neg.
Advertise
Rcv Error
Link Part.
Conf/Stat
Conf/Stat
STATUS
MDINTR
Counter
Counter
PHYID1
PHYID2
Config.
Ability
Name
Rstlh
Aux.
Aux.
Stat
10T
(PIN#)
X
1
0
LP Next
PEND
Reset
4B5B
Page
Page
Rsvd
INTR
Cap.
Next
FDX
100
BP
15
T4
0
1
0
Bit set to logic one
Bit set to logic zero
No default value
Value latched in from pin # at reset
FLP Rcv
TX FDX
Enable
Loop
back
Rsvd
Cap.
SCR
HDX
Ack
Ack
100
BP
LP
LP
14
0
0
0
TX HDX
Remote
Enable
Speed
ALIGN
select
LH_
Rsvd
ISO
Fault
Cap.
FDX
HBE
RF
BP
LP
13
10
0
1
10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver
10 FDX
Auto-N
Enable
Enable
CSTS
DPOK
SQUE
BP_A
Rsvd
LH_
Cap.
HDX
12
10
Reserved
0
1
Reserved
Reserved
10 HDX
Repeat
Enable
Power
Down
mode
Mask
Cap.
JAB
RMII
FDX
LH_
11
0
1
Reserved
Reserved
SCRAM
Isolate Restart
Select
TX/FX
Serial
Mask
SPD
Adv
LH_
10T
FC
LP
FC
10
0
0
Auto-N
Enable
REP
LH_
Mask
Link
Adv
FEF
LP
T4
T4
9
0
Reserved
T5TMOD
Receive Error Counter
TX FDX
TX FDX
Duplex
Enable
LH_
<Access Type>:
<Attribute (s)>:
Mask
INTR
RMII
Adv
Full
LP
8
1
RO = Read only
RW = Read/Write
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
Model No.
TX HDX
TX HDX
100LNK
Force
Rsvd
Coll.
Test
Adv
LP
7
1
PHY ADDR [4:0]
LH_OP [2:0]
10 FDX
10 FDX
Pream.
SPDLE
D_CTL
Supr.
Rsvd
Adv
LP
6
0
Reserved
Compl.
10 HDX
10 HDX
COLLE
Auto-N
D_CTL
Rsvd
Adv
LP
5
0
Disconnect Counter
Remote
RPDCT
Change
Pardet
R-EN
Fault
Fault
FDX
4
0
Link Partner Protocol Selector Field
Advertised Protocol Selector Field
Version: DM9161-DS-F05
LP Next
Pg Able
Change
St. Mch
Auto-N
Reserved
Reset
Cap.
SPD
3
0
DM9161
September 10, 2008
LH_PHYAD [4:0}
Auto-N. Monitor Bit [3:0]
Version No.
Next Pg
Change
Pream.
Status
Supr.
Able
Link
Link
2
0
New Pg
Jabber
Detect
mode
Sleep
Rsvd
Rcv
1
0
Final
LP AutoN
LoopOut
Reverse
Remote
Polarity
Status
INTR
Extd
Cap.
Cap.
0
0