MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 108

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MT29C4G48MAZAPAKD-5 E IT

Manufacturer Part Number
MT29C4G48MAZAPAKD-5 E IT
Description
Manufacturer
Micron
Datasheet
Figure 79: TWO-PLANE BLOCK ERASE
Figure 80: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
WE#
R/B#
I/Ox
CE#
ALE
RE#
CLE
WE#
I/Ox
CE#
ALE
RE#
CLE
60h
Address input (3 cycles)
1st plane
78h
D1h
Optional
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
t DBSY
Address (3 cycles)
60h
108
Address input (3 cycles)
2nd plane
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t WHR
D0h
t AR
Two-Plane Operations
t BERS
t REA
© 2009 Micron Technology, Inc. All rights reserved.
Status output
or 78h
70h
Status
Don‘t Care

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