MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 13

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Note:
Table 1: x8, x16 NAND Ball Descriptions
1. Balls marked RFU may or may not be connected internally. These balls should not be
CE0#, CE1#
used. Contact factory for details.
I/O[15:0]
Symbol
LOCK
WE#
WP#
R/B#
ALE
RE#
CLE
V
CC
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Output Ready/busy: Open-drain, active-LOW output that indicates
output
Supply
Input/
Type
Input
Input
Input
Input
Input
Input
Input
13
Address latch enable: When ALE is HIGH, addresses can be
transferred to the on-chip address register.
Chip enable: Gates transfers between the host system and
the NAND device.
CE1# is used when a second CE# is required and is RFU
other configurations.
Command latch enable: When CLE is HIGH, commands can be
transferred to the on-chip command register.
When LOCK is HIGH during power-up, the BLOCK LOCK func-
tion is enabled. To disable BLOCK LOCK, connect LOCK to V
during power-up, or leave it unconnected (internal pull-down).
Read enable: Gates information from the NAND device to the
host system.
Write enable: Gates information from the host system to the
NAND device.
Write protect: Driving WP# LOW blocks ERASE and
PROGRAM operations.
Data inputs/outputs: The bidirectional I/Os transfer address,
data, and instruction information. Data is output only during
READ operations; at other times the I/Os are inputs.
I/O[15:8] are RFU for x8 NAND devices.
when an internal operation is in progress.
V
CC
: NAND power supply.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
Description
© 2009 Micron Technology, Inc. All rights reserved.
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