MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 196

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 131: Consecutive WRITE-to-WRITE
Figure 132: Nonconsecutive WRITE-to-WRITE
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
Command
Address
Address
DQS
DQS
DQ
DQ
CK#
CK#
DM
DM
CK
CK
3
3
Notes:
Notes:
WRITE
WRITE
Bank,
Bank,
Col b
Col b
T0
T0
1, 2
1, 2
t
1. Each WRITE command can be to any bank.
2. An uninterrupted burst of 4 is shown.
3. D
1. Each WRITE command can be to any bank.
2. An uninterrupted burst of 4 is shown.
3. D
t
DQSS (NOM)
DQSS (NOM)
IN
IN
b (n) = data-in for column b (n).
b (n) = data-in for column b (n).
NOP
NOP
D
D
T1
T1
b
b
IN
IN
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
T1n
T1n
b+1
b+1
D
D
IN
IN
WRITE
Bank,
Col n
b+2
b+2
D
NOP
D
T2
T2
IN
IN
196
1, 2
T2n
b+3
T2n
b+3
D
D
IN
IN
WRITE
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Bank,
NOP
Col n
T3
D
T3
n
IN
1,2
Don’t Care
Don’t Care
T3n
n+1
D
IN
n+2
NOP
D
D
T4
T4
NOP
n
IN
IN
T4n
T4n
n+3
n+1
D
D
IN
IN
Transitioning Data
Transitioning Data
© 2009 Micron Technology, Inc. All rights reserved.
WRITE Operation
n+2
D
T5
NOP
T5
NOP
IN
T5n
n+3
D
IN