MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 200

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 136: WRITE-to-READ – Odd Number of Data, Interrupting
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
DQ
DQ
DQ
CK#
DM
DM
DM
CK
4
5
4
5
4
5
1
WRITE
Bank a,
Col b
T0
Notes:
t
t
t
DQSS
DQSS
DQSS
2
1. An interrupted burst of 4 is shown; 1 data element is written, 3 are masked.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3.
4. DQS is required at T2 and T2n (nominal case) to register DM.
5. D
D
b
IN
t
NOP
WTR is referenced from the first positive CK edge after the last data-in pair.
D
T1
IN
b
IN
b = data-in for column b; D
D
b
IN
T1n
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
NOP
T2
t
WTR
T2n
3
200
Bank a,
READ
Col b
T3
OUT
n = data-out for column n.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T4
NOP
Don’t Care
CL = 3
CL = 3
CL = 3
T5
NOP
© 2009 Micron Technology, Inc. All rights reserved.
WRITE Operation
T5n
Transitioning Data
D
D
D
OUT
n
OUT
n
OUT
n
T6
NOP
D
n + 1
D
n + 1
D
n + 1
OUT
OUT
T6n
OUT