MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 72

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MT29C4G48MAZAPAKD-5 E IT

Manufacturer Part Number
MT29C4G48MAZAPAKD-5 E IT
Description
Manufacturer
Micron
Datasheet
READ PAGE TWO-PLANE 00h-00h-30h
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
The READ PAGE TWO-PLANE (00h-00h-30h) operation is similar to the PAGE READ
(00h-30h) operation. It transfers two pages of data from the NAND Flash array to the
data registers. Each page must be from a different plane on the same die.
To enter the READ PAGE TWO-PLANE mode, write the 00h command to the command
register, and then write five address cycles for plane 0 (BA6 = 0). Next, write the 00h
command to the command register, and five address cycles for plane 1 (BA6 = 1). Final-
ly, issue the 30h command. The first-plane and second-plane addresses must meet the
two-plane addressing requirements, and, in addition, they must have identical column
addresses.
After the 30h command is written, page data is transferred from both planes to their
respective data registers in
fers are complete, R/B# goes HIGH. To read out the data from the plane 0 data register,
pulse RE# repeatedly. After the data cycle from the plane 0 address completes, issue a
RANDOM DATA READ TWO-PLANE (06h-E0h) command to select the plane 1 address,
then repeatedly pulse RE# to read out the data from the plane 1 data register.
Alternatively, the READ STATUS (70h) command can monitor data transfers. When the
transfers are complete, status register bit 6 is set to 1. To read data from the first of the
two planes, the user must first issue the RANDOM DATA READ TWO-PLANE (06h-E0h)
command and pulse RE# repeatedly.
When the data cycle is complete, issue a RANDOM DATA READ TWO-PLANE (06h-E0h)
command to select the other plane. To output the data beginning at the specified col-
umn address, pulse RE# repeatedly.
Use of the READ STATUS ENHANCED (78h) command is prohibited during and follow-
ing a PAGE READ TWO-PLANE operation.
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
t
R. During these transfers, R/B# goes LOW. When the trans-
72
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© 2009 Micron Technology, Inc. All rights reserved.
Read Operations

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