MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 134

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

2Gb: x16, x32 Mobile LPDDR SDRAM
Features
Table 37: Configuration Addressing – 2Gb
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Architecture
Configuration
Refresh count
Row addressing
Column addressing
32 Meg x 16 x 4 banks 16 Meg x 32 x 4 banks
128 Meg x 16
2K A11, A[9:0]
• V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data—one mask per byte
• Programmable burst lengths (BL): 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• Temperature-compensated self refresh (TCSR)
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Status read register (SRR)
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh
16K A[13:0]
architecture; two data accesses per clock cycle
DD
8K
/V
DDQ
= 1.70–1.95V
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
64 Meg x 32
16K A[13:0]
1K A[9:0]
8K
134
2Gb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Option 128 Meg x 16
32 Meg x 16 x 4 banks
Reduced Page-Size
32K A[14:0]
1K A[9:0]
8K
© 2009 Micron Technology, Inc. All rights reserved.
16 Meg x 32 x 4 banks
Option 64 Meg x 32
Reduced Page-Size
32K A[14:0]
512K A[8:0]
8K